DS4000D0/WBGA Maxim Integrated Products, DS4000D0/WBGA Datasheet - Page 13

• Manufacturer Part Number: DS4000D0/WBGA
• Description: IC OSC DC-TCXO 13.00000MHZ TCXO
• Manufacturer: Maxim Integrated Products
• Type: Temperature, Compensated Crystal Oscillator (TCXO)r

Specifications of DS4000D0/WBGA

• Frequency: 13MHz
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 1.5mA
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Count: -

SLAVE ADDRESS
The slave address is the first byte received following the START condition generated by the master device. The
address byte consists of a 7-bit slave address and the R/ W direction bit. The DS4000 slave address is set to
100010A
address to one of two possible address locations. The last bit following the slave address is the direction bit (R/ W )
and defines the operation to be performed by the master, transmit data (R/ W = 0), or receive data (R/ W = 1).
Following the START condition, the DS4000 monitors the SDA bus by checking the slave address being
transmitted. Upon receiving the proper slave address and R/ W bit, the slave device outputs an acknowledge signal
on the SDA line regardless of the operation mode.
The DS4000 can operate in the following two modes:
1) Slave Receiver Mode: Serial data and clock are received through SDA and SCL. After each byte is received,
2) Slave Transmitter Mode: The first byte is received and handled as in the slave receiver mode. However, in
Figure 4. Data Write—Slave Receiver Mode
Figure 5. Data Read—Slave Transmitter Mode
S
S
an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a
serial transfer. Address recognition is performed by the hardware after reception of the slave address and
direction bit (Figure 4).
this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by
the DS4000 while the serial clock is input on SCL. START and STOP conditions are recognized as the
beginning and end of a serial transfer (Figure 5).
S = START
A = ACKNOWLEDGE
P = STOP
S = START
A = ACKNOWLEDGE
P = STOP
A = NOT ACKNOWLEDGE
<
<
SLAVE ADDRESS
SLAVE ADDRESS
100010A
100010A
0
, where A
0
0
>
>
0
is externally hardwired to a HIGH or LOW state. This allows design flexibility to set the slave’s
R/W
R/W
0
1
A
A
<
XXXXXXXX
XXXXXXXX
DATA ADDRESS
<DATA (n)>
>
A
A
XXXXXXXX
XXXXXXXX
<DATA (n + 1)>
<
13 of 16
DATA
(n)>
A
A
P
XXXXXXXX
<DATA (n + 2)>
A
XXXXXXXX
<DATA (n + X)>
A
P