DS1338C-33# Maxim Integrated Products, DS1338C-33# Datasheet - Page 13

• Manufacturer Part Number: DS1338C-33#
• Description: IC RTC 56BIT NV SRAM 16-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAMr

Specifications of DS1338C-33#

• Memory Size: 56B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Function: Clock/Calendar
• Rtc Memory Size: 56 Byte
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial (I2C)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Depending upon the state of the R/W bit, two types of data transfer are possible:
1) Data transfer from a master transmitter to a slave receiver. The master transmits the first byte (the slave
2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave
The DS1338 can operate in the following two modes:
1) Slave receiver mode (write mode): Serial data and clock are received through SDA and SCL. An
2) Slave transmitter mode (read mode): The first byte is received and handled as in the slave receiver mode.
address). Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte.
Data is transferred with the most significant bit (MSB) first.
address). The slave then returns an acknowledge bit, which is followed by the slave transmitting a number of
data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end
of the last received byte, a “not acknowledge” is returned. The master device generates all of the serial clock
pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated
START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is
not released. Data is transferred with the most significant bit (MSB) first.
acknowledge bit is transmitted after each byte is received. START and STOP conditions are recognized as the
beginning and end of a serial transfer. Hardware performs address recognition after reception of the slave
address and direction bit (Figure 6). The slave address byte is the first byte received after the master
generates the START condition. The slave address byte contains the 7-bit DS1338 address—1101000—
followed by the direction bit (R/W), which, for a write, is 0. After receiving and decoding the slave address byte,
the slave outputs an acknowledge on the SDA line. After the DS1338 acknowledges the slave address and
write bit, the master transmits a register address to the DS1338. This sets the register pointer on the DS1338,
with DS1338 acknowledging the transfer. The master may then transmit zero or more bytes of data, with the
DS1338 acknowledging each byte received. The register pointer increments after each data byte is transferred.
The master generates a STOP condition to terminate the data write.
However, in this mode, the direction bit indicates that the transfer direction is reversed. The DS1338 transmits
serial data on SDA while the serial clock is input on SCL. START and STOP conditions are recognized as the
beginning and end of a serial transfer (Figure 7). The slave address byte is the first byte received after the
master generates the START condition. The slave address byte contains the 7-bit DS1338 address—
1101000—followed by the direction bit (R/W), which, for a read, is 1. After receiving and decoding the slave
address byte, the slave outputs an acknowledge on the SDA line. The DS1338 then starts transmitting data
using the register address pointed to by the register pointer. If the register pointer is not set before the initiation
of a read mode, the first address that is read is the last one stored in the register pointer. The register pointer is
incremented after each byte is transferred. The DS1338 must receive a “not acknowledge” to end a read.
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DS1338 I
2
C RTC with 56-Byte NV RAM