DS1670S+ Maxim Integrated Products, DS1670S+ Datasheet - Page 9

• Manufacturer Part Number: DS1670S+
• Description: IC CTRLR SYSTEM PORTABLE 20SOIC
• Manufacturer: Maxim Integrated Products
• Type: Portable System Controllerr

Specifications of DS1670S+

• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: 3-Wire Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Details

DS1670
input that is selected by these 2 bits. Note also that the converter can be turned off by these bits to reduce
power. When the ADC is turned on by setting AIS0 and AIS1 to any value other than 0,0 the analog input
voltage is converted and written to the ADC Register within 488ms. An internal analog filter at the input
reduces high frequency noise. Subsequent updates occur approximately every 10ms. If AIS0 and/or AIS1
are changed, updates will occur at the next 10ms conversion time.
The Conversion Update In Progress (CU) bit in the Status Register indicates when the ADC Register can
be read. When this bit is a 1, an update to the ADC Register will occur within 488ms maximum.
However, when this bit is 0 an update will not occur for at least 244ms. The CU bit should be polled
before reading the ADC Register to ensure that the contents are stable during a read cycle. Once a read
cycle to the ADC Register has been started, the DS1670 will not update that register until the read cycle
has been completed. It should also be mentioned that taking CS low will abort the read cycle and will
allow the ADC Register to be updated.
Figure 6 illustrates the timing of the CU bit relative to an instruction to begin conversion and the
completion of that conversion.
CU BIT TIMING Figure 6
3-WIRE SERIAL INTERFACE
Communication with the DS1670 is accomplished through a simple 3-wire interface consisting of the
Chip Select (CS), Serial Clock (SCLK) and Input/Output (I/O) pins.
All data transfers are initiated by driving the CS input high. The CS input serves two functions. First, CS
turns on the control logic, which allows access to the shift register for the address/command sequence.
Second, the CS signal provides a method of terminating either single byte or multiple byte (burst) data
transfer. A clock cycle is a sequence of a rising edge followed by a falling edge. For data input, data must
be valid during the rising edge of the clock and data bits are output on the falling edge of the clock. If the
CS input goes low, all data transfer terminates and the I/O pin goes to a high-impedance state.
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