DS1744-70IND+ Maxim Integrated Products, DS1744-70IND+ Datasheet

IC RTC RAM Y2K 5V 70NS 28-EDIP

DS1744-70IND+

Manufacturer Part Number
DS1744-70IND+
Description
IC RTC RAM Y2K 5V 70NS 28-EDIP
Manufacturer
Maxim Integrated Products
Type
Clock/Calendar/NVSRAM/Y2Kr
Datasheet

Specifications of DS1744-70IND+

Memory Size
256K (32K x 8)
Time Format
HH:MM:SS (24 hr)
Date Format
YY-MM-DD-dd
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
28-DIP Module (600 mil), 28-EDIP
Function
Clock/Calendar/NV Timekeeping RAM
Rtc Memory Size
32768 Byte
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
Through Hole
Rtc Bus Interface
Parallel
Supply Current
75 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
19-5502; Rev 9/10
FEATURES
 Integrated NV SRAM, Real-Time Clock,
 Clock Registers are Accessed Identically to
 Century Byte Register (i.e., Y2K Compliant)
 Totally Nonvolatile with Over 10 Years of
 BCD-Coded Century, Year, Month, Date,
 Battery Voltage-Level Indicator Flag
 Power-Fail Write Protection Allows for ±10%
 Lithium Energy Source is Electrically
 DIP Module Only
 PowerCap Module Board Only
 Also Available in Industrial Temperature
 UL Recognized
www.maxim-ic.com
Crystal, Power-Fail Control Circuit, and
Lithium Energy Source
the Static RAM. These Registers are Resident
in the Eight Top RAM Locations.
Operation in the Absence of Power
Day, Hours, Minutes, and Seconds with
Automatic Leap-Year Compensation Valid
Up to the Year 2100
V
Disconnected to Retain Freshness Until
Power is Applied for the First Time
Standard JEDEC Byte-Wide 32k x 8 Static
Surface-Mountable Package for Direct
Replaceable Battery (PowerCap)
Power-On Reset Output
Pin-for-Pin Compatible with Other Densities
Range: -40°C to +85°C
CC
RAM Pinout
Connection to PowerCap Containing
Battery and Crystal
of DS174xP Timekeeping RAM
Power-Supply Tolerance
Y2K-Compliant, Nonvolatile Timekeeping RAMs
1 of 18
PIN CONFIGURATIONS
TOP VIEW
GND
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
N.C.
N.C.
N.C.
DQ7
RST
V
WE
OE
CE
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
GND
(Uses DS9034PCX PowerCap)
DQ0
DQ1
DQ2
PowerCap MODULE BOARD
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DS1744P
GND
DS1744
DS1744/DS1744P
EDIP
V
BAT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
X2
V
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
CC
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
N.C.
N.C.
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

Related parts for DS1744-70IND+

DS1744-70IND+ Summary of contents

Page 1

... DQ2 DQ1 DQ0 GND DS1744/DS1744P A14 CC DS1744 A12 A13 A11 A10 DQ7 11 18 DQ0 DQ6 12 17 DQ1 DQ5 13 16 DQ2 DQ4 14 15 GND DQ3 EDIP DS1744P GND BAT PowerCap MODULE BOARD (Uses DS9034PCX PowerCap) N.C. N.C. A14 A13 A12 A11 A10 ...

Page 2

... RST — 33, — N.C. 34 X1, X2, — V BAT DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs FUNCTION Address Input Data Input/Output Ground Active-Low Chip-Enable Input Active-Low Output-Enable Input Active-Low Write-Enable Input Power-Supply Input Active-Low Reset Output, Open Drain. Requires a pullup resistor for proper operation. No Connection ...

Page 3

... ORDERING INFORMATION VOLTAGE PART (V) DS1744-70+ 5.0 DS1744-70IND+ 5.0 DS1744W-120+ 3.3 DS1744W-120IND+ 3.3 DS1744P-70+ 5.0 DS1744P-70IND+ 5.0 DS1744WP-120+ 3.3 DS1744WP-120IND+ 3.3 +Denotes a lead(Pb)-free/RoHS-compliant package. *DS9034-PCX+ or DS9034I-PCX+ required (must be ordered separately). **A “+” anywhere in the top mark denotes a lead-free device. An “IND” denotes an industrial temperature grade device. ...

Page 4

... CLOCK OPERATIONS—READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1744 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. ...

Page 5

... As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit like the read bit, halts updates to the DS1744 registers. The user can then load them with the correct day, date, and time data in 24-hour BCD format. Resetting the write bit then transfers those values to the actual clock counters and allows normal operation to resume ...

Page 6

... WRITING DATA TO RAM OR CLOCK The DS1744 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition The addresses must be held valid throughout the cycle must return inactive for a minimum of t write cycle ...

Page 7

... RST , all control, data, and address signals must be powered down when V BATTERY LONGEVITY The DS1744 has a lithium power source that is designed to provide energy for clock activity and clock and RAM data retention when the V sufficient to power the DS1744 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at +25 ...

Page 8

... Input) Output Leakage Current (Any Output) Output Logic 1 Voltage (I = -1.0mA) OUT Output Logic 0 Voltage (I = +2.1mA) OUT Write Protection Voltage Battery Switchover Voltage DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs TEMP RANGE 0°C to +70°C, Noncondensing -40°C to +85°C, Noncondesnsing SYMBOL MIN -0.3 ...

Page 9

... AC CHARACTERISTICS—READ CYCLE (5V) = 5.0V 10%, (V Over the operating range PARAMETER Read Cycle Time Address Access Time Low-Z CE Access Time CE Data Off Time Low-Z OE Access Time OE Data Off Time Output Hold from Address DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN TYP CC1 I CC2 2.4 ...

Page 10

... Over the operating range PARAMETER Read Cycle Time Address Access Time Low-Z CE Access Time CE Data Off Time Low-Z OE Access Time OE Data Off Time Output Hold from Address READ CYCLE TIMING DIAGRAM DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN TYP t 120 CEL t CEA ...

Page 11

... Write Cycle Time Address Setup Time WE Pulse Width CE Pulse Width CE and CE2 Pulse Width Data Setup Time Data Hold Time Data Hold Time Address Hold Time Address Hold Time WE Data Off Time Write Recovery Time DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN TYP ...

Page 12

... WRITE CYCLE TIMING DIAGRAM, WRITE-ENABLE CONTROLLED WRITE CYCLE TIMING DIAGRAM, CHIP-ENABLE CONTROLLED DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs ...

Page 13

... A PARAMETER Before Power-Down IH V Fall Time PF(MAX) PF(MIN) V Fall Time PF(MIN Rise Time PF(MIN) PF(MAX) Power-Up Recover Time Expected Data-Retention Time (Oscillator ON) POWER-UP/DOWN TIMING (5V DEVICE) DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN TYP 300 REC MAX UNITS NOTES s s s  ...

Page 14

... PF(MAX) PF(MIN) V Rise Time PF(MIN) PF(MAX RST High PF Expected Data-Retention Time (Oscillator ON) POWER-UP/DOWN WAVEFORM TIMING (3.3V DEVICE) CAPACITANCE (T = +25°C) A PARAMETER Capacitance On All Input Pins Capacitance On All Output Pins DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN 300 REC SYMBOL MIN TYP C ...

Page 15

... Battery switchover occurs at the lower of either the battery terminal voltage Data-retention time is at +25C. 6) Each DS1744 has a built-in switch that disconnects the lithium source until the user first applies V The expected t is defined for DIP modules and assembled PowerCap modules as a cumulative time ...

Page 16

... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time  2010 Maxim Integrated Products DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs DESCRIPTION Maxim and the Dallas logo are registered trademarks of Maxim Integrated Products. ...

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