DS1375T+ Maxim Integrated Products, DS1375T+ Datasheet - Page 3

• Manufacturer Part Number: DS1375T+
• Description: IC RTC SERIAL W/ALARM 6-TDFN
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/Alarmr

Specifications of DS1375T+

• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 6-TDFN Exposed Pad
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: I2C
• Supply Current: 33 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

AC ELECTRICAL CHARACTERISTICS
(V
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
SCL Clock Frequency
Bus Free Time Between STOP
and START Conditions
Hold Time (Repeated) START
Condition (Note 8)
Low Period of SCL Clock
High Period of SCL Clock
Data Hold Time (Notes 9, 10)
Data Setup Time (Note 11)
Start Setup Time
Rise Time of Both SDA and SCL
Signals (Note 12)
Fall Time of Both SDA and SCL
Signals (Note 12)
Setup Time for STOP Condition
Capacitive Load for Each Bus
Line (Note 12)
Pulse Width of Spikes that Must
be Suppressed by the Input Filter
CC
= V
CCMIN
PARAMETER
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300ns for the SDA signal (see the V
bridge the undefined region of the falling edge of SCL.
The maximum t
A fast-mode device can be used in a standard-mode system, but the requirement t
This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does
stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t
= 1250ns before the SCL line is released.
C
B
—total capacitance of one bus line in pF.
to V
CCMAX
, T
HD:DAT
A
= -40°C to +85°C, unless otherwise noted.) (Note 1, Figure 1)
is only met if the device does not stretch the low period (t
SYMBOL
t
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STA
SU:STO
t
t
f
t
HIGH
LOW
SCL
BUF
C
t
t
t
SP
R
F
B
I
_____________________________________________________________________
2
C Digital Input RTC with Alarm
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
CONDITIONS
LOW
SU:DAT
) of the SCL signal.
20 + 0.1C
20 + 0.1C
MIN
100
100
250
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
0
0
0
R MAX
IHMIN
≥ 250ns must then be met.
TYP
B
B
+ t
30
of the SCL signal) to
SU:DAT
MAX
1000
400
100
300
300
300
400
0.9
0.9
= 1000 + 250
UNITS
kHz
pF
µs
µs
µs
µs
µs
ns
µs
ns
ns
µs
ns
3