M48T129V-85PM1 STMicroelectronics, M48T129V-85PM1 Datasheet - Page 12

• Manufacturer Part Number: M48T129V-85PM1
• Description: IC TIMEKPR NVRAM 1MBIT 3V 32-DIP
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T129V-85PM1

• Memory Size: 1M (128K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 32-DIP (600 mil) Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2835-5

Clock operations
3
3.1
3.2
3.3
Note:
3.4
Note:
12/28
Clock operations
TIMEKEEPER
The M48T129Y/V offers 16 internal registers which contain TIMEKEEPER
watchdog, interrupt, flag, and control data. These registers are memory locations which
contain external (user accessible) and internal copies of the data (usually referred to as
BiPORT™ TIMEKEEPER cells). The external copies are independent of internal functions
except that they are updated periodically by the simultaneous transfer of the incremented
internal copy. TIMEKEEPER
Reading the clock
Updates to the TIMEKEEPER
prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are
only data registers and not the actual clock counters, so updating the registers can be halted
without disturbing the clock itself.
Updating is halted when a '1' is written to the READ bit, D6 in the control register (1FFF8h).
As long as a '1' remains in that position, updating is halted. After a halt is issued, the
registers reflect the count; that is, the day, date, and time that were current at the moment
the halt command was issued. All of the TIMEKEEPER
simultaneously. A halt will not interrupt an update in progress. Updating occurs 1 second
after the READ bit is reset to a '0.'
Setting the clock
Bit D7 of the control register (1FFF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like
the READ bit, halts updates to the TIMEKEEPER
with the correct day, date, and time data in 24-hour BCD format (see
Resetting the WRITE bit to a '0' then transfers the values of all time registers (1FFFFh-
1FFF9h, 1FFF1h) to the actual TIMEKEEPER
resume. After the WRITE bit is reset, the next clock update will occur approximately one
second later.
Upon power-up following a power failure, both the WRITE bit and the READ bit will be reset
to '0.'
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP bit is located at bit D7 within 1FFF9h. Setting it to a '1' stops the
oscillator. When reset to a '0', the M48T129Y/V oscillator starts within one second.
It is not necessary to set the WRITE bit when setting or resetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).
®
registers
®
®
and alarm registers store data in BCD.
Doc ID 5710 Rev 4
registers should be halted before clock data is read to
®
counters and allows normal operation to
®
registers. The user can then load them
®
registers are updated
M48T129V, M48T129Y
Table 5 on page
®
, alarm,
13).