DS1338U-3+T&R Maxim Integrated Products, DS1338U-3+T&R Datasheet - Page 9
![IC RTC 56BYTE NV RAM 3V 8-USOP](/photos/1/39/13936/406-8-msop_sml.jpg)
DS1338U-3+T&R
Manufacturer Part Number
DS1338U-3+T&R
Description
IC RTC 56BYTE NV RAM 3V 8-USOP
Manufacturer
Maxim Integrated Products
Type
Clock/Calendar/NVSRAMr
Datasheet
1.DS1338Z-33.pdf
(16 pages)
Specifications of DS1338U-3+T&R
Memory Size
56B
Time Format
HH:MM:SS (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 3.3 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between
the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Crystal
frequency drift caused by temperature shifts creates additional error. External circuit noise coupled into the
oscillator circuit can result in the clock running fast. Figure 4 shows a typical PC board layout for isolating the
crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks
for detailed information.
DS1338C ONLY
The DS1338C integrates a standard 32,768Hz crystal in the package. Typical accuracy at nominal V
is approximately 10ppm. Refer to Application Note 58 for information about crystal accuracy vs. temperature.
Figure 4. Typical PC Board Layout for Crystal
RTC AND RAM ADDRESS MAP
Table 3 shows the address map for the RTC and RAM registers. The RTC registers and control register are located
in address locations 00h to 07h. The RAM registers are located in address locations 08h to 3Fh. During a multibyte
access, when the register pointer reaches 3Fh (the end of RAM space) it wraps around to location 00h (the
beginning of the clock space). On an I
current time and date is transferred to a second set of registers. The time and date in the secondary registers are
read in a multibyte data transfer, while the clock continues to run. This eliminates the need to re-read the registers
in case of an update of the main registers during a read.
CLOCK AND CALENDAR
The time and calendar information is obtained by reading the appropriate register bytes. See Figure 6 for the RTC
registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the
time and calendar registers are in the BCD format. Bit 7 of Register 0 is the clock halt (CH) bit. When this bit is set
to 1, the oscillator is disabled. When cleared to 0, the oscillator is enabled. The clock can be halted whenever the
timekeeping functions are not required, which minimizes V
The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but
must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries
result in undefined operation.
When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the
internal registers update. When reading the time and date registers, the user buffers are synchronized to the
internal registers on any start or stop and when the register pointer rolls over to zero. The countdown chain is reset
NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED
AREA (UPPER LEFT-HAND QUADRANT) OF THE PACKAGE
UNLESS THERE IS A GROUND PLANE BETWEEN THE SIGNAL
LINE AND THE PACKAGE.
LOCAL GROUND PLANE (LAYER 2)
CRYSTAL
GND
X1
X2
2
C START, STOP, or register pointer incrementing to location 00h, the
9 of 16
BAT
current (I
BATDAT
DS1338 I
) when VCC is not applied.
2
C RTC with 56-Byte NV RAM
CC
and +25°C