DS1644-120+ Maxim Integrated Products, DS1644-120+ Datasheet - Page 3
![IC RAM TIMEKEEP NV 120NS 28-EDIP](/photos/6/58/65855/ds1225ab-200__sml.jpg)
DS1644-120+
Manufacturer Part Number
DS1644-120+
Description
IC RAM TIMEKEEP NV 120NS 28-EDIP
Manufacturer
Maxim Integrated Products
Type
Clock/Calendar/NVSRAMr
Datasheet
1.DS1644P-120.pdf
(14 pages)
Specifications of DS1644-120+
Memory Size
256K (32K x 8)
Time Format
HH:MM:SS (24 hr)
Date Format
YY-MM-DD-dd
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
28-DIP Module (600 mil), 28-EDIP
Function
Clock/Calendar/NV Timekeeping RAM
Rtc Memory Size
32768 Byte
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
Through Hole
Rtc Bus Interface
Parallel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PACKAGES
The DS1644 is available in two packages (28-pin DIP and 34-pin PowerCap module). The 28-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1644P after the completion of the surface-mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1644 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.
As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was present at the moment the halt command was issued. However,
the internal clock registers of the double-buffered system continue to update so that the clock accuracy is
not affected by the access of data. All of the DS1644 registers are updated simultaneously after the clock
status is reset. Updating is within a second after the read bit is written to 0.
DS1644 BLOCK DIAGRAM Figure 1
DS1644 TRUTH TABLE Table 1
V
5V 10%
<4.5V >V
<V
CC
BAT
BAT
V
X
V
V
V
X
X
CE
IH
IL
IL
IL
X
X
X
V
V
X
X
OE
IL
IH
X
X
V
V
V
X
X
WE
IL
IH
IH
3 of 14
MODE
DESELECT
DESELECT
WRITE
READ
READ
DESELECT
DESELECT
DQ
HIGH-Z
HIGH-Z
DATA IN
DATA OUT
HIGH-Z
HIGH-Z
HIGH-Z
POWER
STANDBY
STANDBY
ACTIVE
ACTIVE
ACTIVE
CMOS STANDBY
DATA RETENTION
MODE
DS1644/DS1644P