DS1554-70+ Maxim Integrated Products, DS1554-70+ Datasheet
DS1554-70+
Specifications of DS1554-70+
Related parts for DS1554-70+
DS1554-70+ Summary of contents
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... GND 16 Encapsulated DIP IRQ/FT 1 Maxim 2 N.C. 3 DS1554 N.C. RST DQ7 10 DQ6 11 DQ5 12 DQ4 13 DQ3 14 DQ2 15 DQ1 16 DQ0 X1 GND 17 GND PowerCap Module Board (Uses DS9034PCX PowerCap DS1554 N.C. 31 IRQ/ A13 A11 A10 DQ7 20 DQ6 19 DQ5 18 DQ4 17 DQ3 34 N.C. 33 N.C. 32 A14 31 A13 30 A12 29 ...
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... CC GND - Ground N. Connection X1 Crystal Connection V - Battery Connection BAT ORDERING INFORMATION PART TEMP RANGE DS1554-70+ 0°C to +70°C DS1554-70IND+ -40°C to +85°C DS1554P-70+ 0°C to +70°C DS1554P-70IND+ -40°C to +85°C DS1554W-120+ 0°C to +70°C DS1554W-120IND+ -40°C to +85°C DS1554WP-120+ 0°C to +70°C DS1554WP-120IND+ -40° ...
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... RTC alarm, watchdog timer, power-on reset, battery monitor, and 32k x 8 nonvolatile static RAM. User access to all registers within the DS1554 is accomplished with a byte-wide interface as shown in Figure 1. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour binary-coded decimal (BCD) format ...
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... Figure 1. Block Diagram Table 1. Operating Modes > < V < <V < DS1554 256k, Nonvolatile, Y2K-Compliant Timekeeping RAM WE DQ0–DQ7 X X High OUT V High High High Maxim DS1554 MODE POWER Deselect Standby Write Active Read Active Read Active Deselect CMOS Standby Data Retention Battery Current ...
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... DATA-WRITE MODE The DS1554 is in the write mode whenever WE and CE are in their active state. The start of a write is referenced to the latter occurring transition CE. The addresses must be held valid throughout the cycle. CE and WE must return inactive for a minimum write cycle ...
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... The DS1554 has a lithium power source that is designed to provide energy for the clock activity, and clock and RAM data retention when the V supply is sufficient to power the DS1554 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at 25C with the internal clock oscillator running in the absence of V source disconnected, guaranteeing full energy capacity ...
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... The OSC bit is the MSB of the Seconds Register (B7 of 7FF9h). Setting stops the oscillator, setting starts the oscillator. The DS1554 is shipped from Maxim with the clock oscillator turned off, OSC bit set READING THE CLOCK When reading the RTC data recommended to halt updates to the external set of double-buffered RTC Registers ...
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... The alarm can be programmed to activate on a specific day of the month or repeat every day, hour, minute, or second. It can also be programmed to go off while the DS1554 is in the battery-backed state of operation to serve as a system wakeup. Alarm mask bits AM1 to AM4 control the alarm mode. Table 3 shows the possible settings ...
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... AF. Therefore, the AF bit can be read after system power-up to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates alarm timing during the battery-backup mode and power-up states. DS1554 256k, Nonvolatile, Y2K-Compliant Timekeeping RAM AM1 ALARM RATE ...
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... POWER-ON DEFAULT STATES Upon application of power to the device, the following register bits are set to 0: WDS = 0, BMB0 to BMB4 = 0, RB0 to RB1 = and ABE = 0. DS1554 256k, Nonvolatile, Y2K-Compliant Timekeeping RAM /FT output when the watchdog times out ...
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... Input Leakage Current (Any Input) Output Leakage Current (Any Output) Output Logic 1 Voltage (I = -1.0 mA) OUT Output Logic 0 Voltage Write Protection Voltage Battery Switchover Voltage V DS1554 256k, Nonvolatile, Y2K-Compliant Timekeeping RAM TEMP RANGE 0°C to +70°C -40°C to +85°C CONDITIONS = 5V 10 3.3V 10% V ...
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... Input) Output Leakage Current (Any Output) Output Logic 1 Voltage (I = -1.0 mA) OUT Output Logic 0 Voltage Write Protection Voltage Battery Switchover Voltage Figure 5. Read Cycle Timing Diagram DS1554 256k, Nonvolatile, Y2K-Compliant Timekeeping RAM SYMBOL CONDITIONS I (Notes (Notes 2, 3) CC1 I (Notes 2, 3) ...
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... Address Access Time Pulse Width WE Pulse Width CE Data Setup Time Data Hold Time (Note 9) Data Hold Time (Note 10) Address Hold Time (Note 9) Address Hold Time (Note 10) Data Off Time WE Write Recovery Time DS1554 256k, Nonvolatile, Y2K-Compliant Timekeeping RAM = 5.0V 10 SYMBOL MIN MAX ...
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... Figure 6. Write Cycle Timing, Write-Enable Controlled Figure 7. Write Cycle Timing, Chip-Enable Controlled DS1554 256k, Nonvolatile, Y2K-Compliant Timekeeping RAM ...
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... Power-Down V Fall Time PF(MAX) PF(MIN) V Fall Time PF(MIN Rise Time PF(MIN) PF(MAX High RST PF Expected Data-Retention Time (Oscillator On) Figure 8. Power-Up/Down Waveform Timing (5V Device ) DS1554 256k, Nonvolatile, Y2K-Compliant Timekeeping RAM SYMBOL CONDITIONS REC t (Notes MIN TYP MAX UNITS s 0 s 300 s 10 ...
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... PF(MIN) PF(MAX High RST PF Expected Data-Retention Time (Oscillator On) Figure 9. Power-Up/Down Waveform Timing (3.3V Device) CAPACITANCE (T = +25°C) A PARAMETER Capacitance on All Input Pins Capacitance on IRQ/FT, RST, and DQ Pins DS1554 256k, Nonvolatile, Y2K-Compliant Timekeeping RAM SYMBOL CONDITIONS REC t (Notes SYMBOL CONDITIONS C (Note 1) IN ...
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... Battery switchover occurs at the lower of either the battery voltage or V /FT and RST outputs are open drain. 5) The IRQ 6) Data-retention time is at +25C. 7) Each DS1554 has a built-in switch that disconnects the lithium source until V user. The expected t is defined for DIP modules and PowerCap modules as a cumulative time in the DR absence of V starting from the time power is first applied by the user ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time 2010 Maxim Integrated Products DS1554 256k, Nonvolatile, Y2K-Compliant Timekeeping RAM DESCRIPTION parameter in the DC Electrical Characteristics tables Maxim and the Dallas logo are registered trademarks of Maxim Integrated Products ...