DS1747-70+ Maxim Integrated Products, DS1747-70+ Datasheet

IC RTC RAM Y2K 5V 70NS 32-EDIP

DS1747-70+

Manufacturer Part Number
DS1747-70+
Description
IC RTC RAM Y2K 5V 70NS 32-EDIP
Manufacturer
Maxim Integrated Products
Type
Clock/Calendar/NVSRAM/Y2Kr
Datasheet

Specifications of DS1747-70+

Memory Size
4M (512K x 8)
Time Format
HH:MM:SS (24 hr)
Date Format
YY-MM-DD-dd
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
32-DIP Module (600 mil), 32-EDIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
FEATURES
 Integrated NV SRAM, Real-Time Clock
 Clock Registers are Accessed Identically to
 Century Byte Register (Y2K Compliant)
 Totally Nonvolatile with Over 10 Years of
 BCD-Coded Century, Year, Month, Date,
 Battery Voltage-Level Indicator Flag
 Power-Fail Write Protection Allows for
 Lithium Energy Source is Electrically
 DIP Module Only:
 PowerCap Module Board Only:
 Also Available in Industrial Temperature
www.maxim-ic.com
19-5504; Rev 9/10
(RTC), Crystal, Power-Fail Control
Circuit, and Lithium Energy Source
the Static RAM. These Registers are
Resident in the Eight Top RAM Locations
Operation in the Absence of Power
Day, Hours, Minutes, and Seconds with
Automatic Leap Year Compensation Valid
Up to the Year 2100
±10% V
Disconnected to Retain Freshness Until
Power is Applied for the First Time
Standard JEDEC Byte-Wide 512k x 8 Static
Surface-Mountable Package for Direct
Replaceable Battery (PowerCap)
Power-On Reset Output
Pin-for-Pin Compatible with Other Densities
Range: -40°C to +85°C
RAM Pinout
Connection to PowerCap Containing
Battery and Crystal
of DS174xP Timekeeping RAM
CC
Power-Supply Tolerance
Y2K-Compliant, Nonvolatile Timekeeping RAMs
1 of 16
PIN CONFIGURATIONS
GND
TOP VIEW
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
N.C.
DQ7
A15
A16
RST
V
WE
OE
CE
CC
GND
DQ0
DQ1
DQ2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A16
A14
A12
A18
(Uses DS9034PCX PowerCap)
A7
A6
A5
A4
A3
A2
A1
A0
PowerCap Module Board
X1
Encapsulated DIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
(512k x 8)
DS1747
DS1747P
Maxim
Maxim
DS1747/DS1747P
V
BAT
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
X2
V
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
CC
A18
A17
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

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DS1747-70+ Summary of contents

Page 1

... Maxim 2 DS1747 A14 A17 A12 4 29 A13 A11 A10 DQ7 DQ0 DQ6 14 19 DQ1 DQ5 DQ2 15 18 DQ4 17 GND 16 DQ3 Encapsulated DIP (512k Maxim 33 2 DS1747P GND BAT PowerCap Module Board (Uses DS9034PCX PowerCap) A18 A17 A14 A13 A12 A11 A10 ...

Page 2

... Pin Configuration) (See Pin — Configuration) DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs NAME FUNCTION A18 A16 A14 A12 Address Input A10 A11 A9 A8 A13 A17 A15 DQ0 DQ1 DQ2 DQ3 Data Input/Output DQ4 DQ5 DQ6 DQ7 GND Ground ...

Page 3

... PIN-PACKAGE TOP MARK 32 EDIP (0.740a) DS1747-70+ 32 EDIP (0.740a) DS1747-70IND+ 34 PowerCap* DS1747P+70 34 PowerCap* DS1747P+70 IND 32 EDIP (0.740a) DS1747W-120+ 32 EDIP (0.740a) DS1747W-120IND+ 34 PowerCap* DS1747WP+120 ...

Page 4

... CLOCK OPERATIONS—READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1747 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy ...

Page 5

... As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a one, like the read bit, halts updates to the DS1747 registers. The user can then load them with the correct day, date and time data in 24-hour format. Resetting the write bit to a zero then transfers those values to the actual clock counters and allows normal operation to resume ...

Page 6

... OH WRITING DATA TO RAM OR CLOCK The DS1747 is in the write mode whenever WE, and CE are in their active state. The start of a write is referenced to the latter occurring transition CE. The addresses must be held valid throughout the cycle must return inactive for a minimum of t write cycle ...

Page 7

... The DS1747 has a lithium power source that is designed to provide energy for clock activity, and clock and RAM data retention when the V is sufficient to power the DS1747 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at +25C with the internal clock oscillator running in the absence of V power ...

Page 8

... CE  0.2V) CC Input Leakage Current (Any Input) Output Leakage Current (Any Output) Output Logic 1 Voltage (I = -1.0mA) OUT Output Logic 0 Voltage (I = +2.1mA) OUT Write Protection Voltage Battery Switchover Voltage DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN TYP -0.3 IL SYMBOL ...

Page 9

... AC CHARACTERISTICS—READ CYCLE (5V) = 5.0V 10 Over the Operating Range PARAMETER Read Cycle Time Address Access Time Low Access Time CE Data Off Time Low-Z OE Access Time OE Data Off Time Output Hold from Address DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN TYP Icc Icc 1 Icc ...

Page 10

... Over the Operating Range PARAMETER Read Cycle Time Address Access Time Low Access Time CE Data Off Time Low-Z OE Access Time OE Data Off Time Output Hold from Address READ CYCLE TIMING DIAGRAM DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN TYP t 120 CEL t CEA ...

Page 11

... Write Cycle Time Address Setup Time WE Pulse Width CE Pulse Width CE and CE2 Pulse Width Data Setup Time Data Hold Time Data Hold Time Address Hold Time Address Hold Time WE Data Off Time Write Recovery Time DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN TYP ...

Page 12

... WRITE CYCLE TIMING DIAGRAM, WRITE-ENABLE CONTROLLED WRITE CYCLE TIMING DIAGRAM, CHIP-ENABLE CONTROLLED DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs ...

Page 13

... Fall Time PF(MAX) V PF(MIN) V Fall Time PF(MIN Rise Time PF(MIN MAX) Power-Up Recover Time VPF to RST High (PowerCap Only) Expected Data-Retention Time (Oscillator ON) POWER-UP/DOWN TIMING (5V DEVICE) DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN TYP 300 REC MAX UNITS NOTES s s  ...

Page 14

... PF(MAX) Power-Up Recover Time V to RST High (PowerCap PF Only) Expected Data-Retention Time (Oscillator ON) POWER-UP/DOWN WAVEFORM TIMING (3.3V DEVICE) CAPACITANCE (T = +25°C) A PARAMETER Capacitance on All Input Pins Capacitance on All Output Pins DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs SYMBOL MIN TYP 300 REC t 10 ...

Page 15

... Battery switchover occurs at the lower of either the battery terminal voltage Data-retention time is at +25C. 6) Each DS1747 has a built-in switch that disconnects the lithium source until the user first applies V The expected t is defined for DIP modules and assembled PowerCap modules as accumulative time ...

Page 16

... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time  2010 Maxim Integrated Products DS1747/DS1747P Y2K-Compliant, Nonvolatile Timekeeping RAMs DESCRIPTION Maxim and the Dallas logo are registered trademarks of Maxim Integrated Products. ...

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