X1288V14Z-2.7A Intersil, X1288V14Z-2.7A Datasheet - Page 11
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X1288V14Z-2.7A
Manufacturer Part Number
X1288V14Z-2.7A
Description
IC RTC/CAL/CPU SUPERVSR 14-TSSOP
Manufacturer
Intersil
Type
Clock/Calendar/Supervisor/EEPROMr
Datasheet
1.X1288S16.pdf
(27 pages)
Specifications of X1288V14Z-2.7A
Memory Size
256K (32K x 8)
Time Format
HH:MM:SS:hh (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 1. Clock/Control Memory Map
ALARM REGISTERS
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
– Setting the Enable Month bit (EMOn*) bit in combi-
*n = 0 for Alarm 0: N = 1 for Alarm 1
When there is a match, an alarm flag is set. The occur-
rence of an alarm can be determined by polling the
AL0 and AL1 bits or by enabling the IRQ output, using
it as hardware flag.
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
Addr.
003F
000F
000E
000D
000C
000B
000A
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
Control (EE-
(EEPROM)
(EEPROM)
(SRAM)
PROM)
Alarm1
Alarm0
Status
Type
RTC
DWA1
MOA1
MNA1
DWA0
MOA0
MNA0
Name
SSEC
HRA1
HRA0
YRA1
DTA1
SCA1
YRA0
DTA0
SCA0
Y2K1
Y2K0
DTR
Reg
ATR
DW
MO
INT
HR
MN
SR
YR
DT
SC
BL
11
EDW1
EDW0
EMO1
EMN1
EMO0
EMN0
EHR1
ESC1
EHR0
ESC0
SS23
EDT1
EDT0
BAT
BP2
Y23
MIL
IM
0
0
0
0
0
0
0
7
Unused - Default = RTC Year value (No EEPROM) – Future expansion
Unused - Default = RTC Year value (No EEPROM) - Future expansion
A1M22
A0M22
A1S22
A0S22
SS22
AL1E
M22
BP1
AL1
Y22
S22
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A1M21
A0M21
A1D21
A1H21
A1S21
A0D21
A0H21
A0S21
ATR5
SS21
AL0E
D21
H21
M21
BP0
AL0
Y21
S21
5
0
0
0
0
0
0
0
Read-only - Default = 20h
Read-only - Default = 20h
X1288
A1M20
A0M20
A1G20
A1D20
A1H20
A1S20
A0G20
A0D20
A0H20
A0S20
SS20
ATR4
WD1
G20
D20
H20
M20
FO1
Y20
S20
4
0
0
0
0
0
– The user can set the X1288 to alarm every Wednes-
– A daily alarm for 9:30PM results when the EHRn*
*n = 0 for Alarm 0: N = 1 for Alarm 1
REAL TIME CLOCK REGISTERS
Clock/Calendar Registers (SSEC, SC, MN, HR, DT,
MO, YR)
These registers depict BCD representations of the
time. As such, SSEC (1/100 Second) range from 00 to
99, SC (Seconds) and MN (Minutes) range from 00 to
59, HR (Hour) is 1 to 12 with an AM or PM indicator
Bit
day at 8:00 AM by setting the EDWn*, the EHRn*
and EMNn* enable bits to ‘1’ and setting the DWAn*,
HRAn* and MNAn* Alarm registers to 8:00 AM
Wednesday.
and EMNn* enable bits are set to ‘1’ and the HRAn*
and MNAn* registers are set to 9:30 PM.
A1M13
A0M13
A1G13
A1D13
A1H13
A0G13
A0D13
A0H13
A1S13
A0S13
SS13
ATR3
WD0
G13
M13
FO0
Y13
D13
H13
S13
3
0
0
0
0
0
Read Only Read Only Read Only
Read Only Read Only Read Only
A1G12
A1D12
A1H12
A1M12
A0G12
A0D12
A0H12
A0M12
RWEL
A1S12
A0S12
DTR2
SS12
ATR2
DY2
G12
M12
DY2
DY2
Y12
D12
H12
S12
2
A1G11
A1D11
A1H11
A1M11
A0G11
A0D11
A0H11
A0M11
A1S11
A0S11
DTR1
ATR1
SS11
WEL
DY1
G11
M11
DY1
DY1
Y11
D11
H11
S11
1
(optional)
A1G10
A1D10
A1H10
A1M10
A0G10
A0D10
A0H10
A0M10
A1S10
A0S10
RTCF
DTR0
ATR0
SS10
DY0
G10
M10
DY0
DY0
Y10
D10
H10
S10
0
Range
0-99
0-99
1-12
1-31
0-23
0-59
0-59
1-12
1-31
0-23
0-59
0-59
1-12
1-31
0-23
0-59
0-59
0-6
0-6
0-6
20
20
April 14, 2006
FN8102.3
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