DS1689 Maxim Integrated Products, DS1689 Datasheet
DS1689
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DS1689 Summary of contents
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... Output for Power Management 32-Bit V 32-Bit V 16-Bit Power Cycle Counter Compatible with Existing BIOS for Original DS1287 Functions Available as IC (DS1689) or Stand-Alone Module with Embedded Battery and Crystal (DS1693) Available in Industrial Temperature Version Timekeeping Algorithm Includes Leap Year Compensation Valid Up to 2100 ...
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... For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real Time Clocks. The DS1689 can also be driven by an external 32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. ...
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... KS pin can be used as an interrupt input. Active-Low Chip Select Input. This signal must be asserted low during a bus cycle for the RTC portion of the DS1689/DS1693 to be accessed. CS must be kept in the active state during RD and WR timing. Bus cycles, which take place with ALE asserted but without asserting, CS will latch addresses ...
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PIN NAME SO EDIP 24 24 SQW CCO CCI 27 27 CEO 28 28 CEI 2, 3, — N.C. 19, 23 FUNCTION Square-Wave Output. The SQW pin can output a signal from one of ...
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... The DS1689 is a clock/calendar chip with the features described above. An external crystal and battery are the only components required to maintain time-of-day and memory status in the absence of power. The DS1693 incorporates the DS1689 chip, a 32.768kHz crystal, and a lithium battery in a complete, self- contained timekeeping module. The entire unit is fully tested at Dallas Semiconductor such that a ...
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... Figure 1. DS1689/DS1693 Block Diagram ...
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... REC reset (see Register A). This time period allows the system to stabilize after power is applied. When PSEL is floating or logic 0, the DS1689 is in autosense mode and operation is determined based on the voltage on V rises above 4.5V for a minimum of t rise above the level of 4 ...
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... Figure 2. DS1689 Real-Time Clock Address Map TIME, CALENDAR, AND ALARM LOCATIONS The time and calendar information is obtained by reading the appropriate register bytes shown in Table 1. The time, calendar, and alarm are set or initialized by writing the appropriate register bytes. The contents of the time, calendar, and alarm registers can be either Binary or Binary-Coded Decimal (BCD) format. ...
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... NONVOLATILE RAM—RTC The 114 general-purpose nonvolatile RAM bytes are not dedicated to any special function within the DS1689/DS1693. They can be used by the application program as nonvolatile memory and are fully available during the update cycle. This memory is directly accessible when bank 0 is selected. ...
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... The IRQF bit in Register whenever the IRQ pin is being driven low as a result of one of the six possible active sources. Therefore, determination that the DS1689/DS1693 initiated an interrupt is accomplished by reading Register C and finding IRQF = 1. IRQF remains set until all enabled interrupt flag bits are cleared to 0. ...
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A pattern of 01X in the DV2, DV1, and DV0, bits respectively, turns the oscillator on and enables the countdown chain. Note that this is different than the DS1287, which required a pattern of 010 in these bits. DV0 is ...
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Table 2. Periodic Interrupt Rate and Square-Wave Output Frequency EXT. REG. B SELECT BITS REGISTER A E32K RS3 ...
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REGISTER A MSB BIT 7 BIT 6 UIP DV2 Bit 7: UIP (Update In Progress). This bit is a status flag that can be monitored. When the UIP bit is 1, the update transfer will soon occur. When UIP is ...
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... PIE bit blocks the IRQ output from being driven by a periodic interrupt, but the periodic flag (PF) bit is still set at the periodic rate. PIE is not modified by any internal DS1689/DS1693 functions. Bit 5: AIE (Alarm Interrupt Enable). This bit is a read/write bit which, when set to 1, permits the alarm flag (AF) bit in Register C to assert IRQ. An alarm interrupt occurs for each second that the three time bytes equal the three alarm bytes, including a don’ ...
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REGISTER C MSB BIT 7 BIT 6 IRQF PF Bit 7: IRQF (Interrupt Request Flag). This bit is set to 1 when one or more of the following are true PIE = AIE = 1 ...
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... RAM are in the same locations as for the DS1287 result, existing routines implemented within BIOS, DOS, or application software packages can gain access to the DS1689/DS1693 clock registers with no changes. Also in bank 0, an extra 64 bytes of RAM are provided at addresses just above the original locations for a total of 114 directly addressable bytes of user RAM ...
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... Figure 4. DS1689/DS1693 Extended Register Bank Definition ...
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... V battery power is enabled, and when cleared the DS1689/DS1693, this auxiliary battery can be used as the primary backup power source for maintaining the clock/calendar, user RAM, and extended external RAM functions. This occurs if the ...
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... AIE bit (bank 0, register B, 0BH). When the match condition occurs, the PWR pin is automatically driven low. This output can be used to turn on the main system power supply, which provides V voltage to the DS1689/DS1693 as well as the other major components in the system. Also at this time, the wake-up flag (WF, bank 1, register 04AH) is set, indicating that a wake-up condition has occurred. ...
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... PWR and IRQ are tri-stated, and monitoring of wake-up and kickstart takes place. RAM CLEAR The DS1689/DS1693 provide a RAM clear function for the 114 bytes of user RAM. When enabled, this function can be performed regardless of the condition of the V The RAM clear function is enabled or disabled via the RAM Clear Enable bit (RCE; bank 1, register 04BH) ...
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... EXTENDED CONTROL REGISTERS Two extended control registers are provided to supply controls and status information for the extended features offered by the DS1689/DS1693. These are designated as extended control registers A and B and are located in register bank 1, locations 04AH and 04BH, respectively. The functions of the bits within these registers are described as follows ...
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... RAM. When RCE = 0, the RAM clear function is disabled. Bit 3: PRS (PAB Reset Select). When set to 0 the PWR pin is set high impedance when the DS1689 goes into power-fail. When set to 1, the PWR pin remains active upon entering power-fail. ...
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... DS1689/DS1693 and external RAM for the useful life of most equipment. POWER-CYCLE COUNTER The DS1689/DS1693 has a 16-bit power-cycle counter that resides in register 5C and 5D of bank 1. The LSB of this counter resides in 5C and the MSB is in 5D. This binary counter is incremented by one count each time V power is applied within nominal limits. This counter can be read or written at the user’ ...
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ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………..-0.3V to +7.0V Storage Temperature Range………………………………………………………………...-40°C to +70°C Soldering Temperature………………………………………………...260°C for 10 seconds (See Note 18) Soldering Temperature (Surface Mount)…………………………….See IPC/JEDEC J-STD-020 Standard This is a stress rating only and ...
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DC ELECTRICAL CHARACTERISTICS—5V (Over the operating range.) PARAMETER Average V Power-Supply Current CC CMOS Standby Current ( 0.2V) CC Input Leakage Current (Any Input) CEI Input Leakage PSEL Input Leakage Output Leakage Current Output Logic 1 Voltage ...
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DC ELECTRICAL CHARACTERISTICS—3V (Over the operating range.) PARAMETER Average V Power-Supply Current CC CMOS Standby Current ( 0.2V) CC Input Leakage Current (Any Input) CEI Input Leakage PSEL Input Leakage Output Leakage Current Output Logic 1 Voltage ...
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... High Setup to ALE Rise Pulse Width, ALE High ALE Low Setup Fall Output Data Delay Time from RD Data Setup Time IRQ Release from RD CEI to CEO Delay DS1689/DS1693 BUS TIMING FOR WRITE CYCLE TO RTC AND RTC REGISTERS SYMBOL MIN TYP t 305 CYC ...
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... Muxed Address Hold Time from ALE Fall High Setup to ALE Rise Pulse Width, ALE High ALE Low Setup Fall Output Data Delay Time from RD Data Setup Time IRQ Release from RD CEI to CEO Delay DS1689/DS1693 BUS TIMING FOR READ CYCLE TO RTC SYMBOL MIN TYP t 915 CYC PW ...
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POWER-UP/POWER-DOWN TIMING— +25°C) A PARAMETER CS High to Power-Fail Recovery at Power-Up V Slew Rate Power-Down CC V Slew Rate Power-Down CC V Slew Rate Power-Up CC Expected Data Retention POWER-UP/POWER-DOWN TIMING— +25°C) A PARAMETER CS ...
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POWER-UP CONDITION—5V OPERATION POWER-DOWN CONDITION—5V OPERATION ...
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POWER-UP CONDITION—3V OPERATION POWER-DOWN CONDITION—3V OPERATION ...
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WAKE-UP/KICKSTART TIMING (T = +25°C) A PARAMETER Kickstart Input Pulse Width Wake-Up/Kickstart Power-On Timeout WAKE-UP/KICKSTART TIMING NOTE: TIME INTERVALS SHOWN ABOVE ARE REFERENCED IN WAKE-UP/KICKSTART SECTION. *THIS CONDITION CAN OCCUR WHEN THE DEVICE IS OPERATED IN 3V MODE. SYMBOL MIN ...
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NOTES: 1) All voltages are referenced to ground. 2) Typical values are at +25°C and nominal supplies. 3) Outputs are open. 4) Value for voltage and currents is from the V 5) Write protection trip point occurs during power fail ...
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PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo ...
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PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo ...
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... No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation © 2005 Maxim Integrated Products • Printed USA DS1689/DS1693 ...