AD73322AR-REEL Analog Devices Inc, AD73322AR-REEL Datasheet - Page 28

• Manufacturer Part Number: AD73322AR-REEL
• Description: IC ANALOG FRONT END DUAL 28-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD73322AR-REEL

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-SOIC (7.5mm Width)
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 3.3V
• Package Type: SOIC W
• Lead Free Status / RoHS Status: Not Compliant

AD73322
The device features an on-chip master clock divider circuit that
allows the sample rate to be reduced as the sampling rate of the
sigma-delta converter is proportional to the output of the MCLK
Divider (whose default state is divide by 1).
The decimator’s frequency response (Sinc3) gives some pass-
band attenuation (up to F
the Nyquist frequency. If it is required to implement a digital
filter to create a sharper cutoff characteristic, it may be prudent
to use an initial sample rate of greater than twice the Nyquist
rate in order to avoid aliasing due to the smooth roll-off of the
Sinc3 filter response.
In the case of voiceband processing where 4 kHz represents the
Nyquist frequency, if the signal to be measured were externally
bandlimited then an 8 kHz sampling rate would suffice. How-
ever if it is required to limit the bandwidth using a digital filter,
then it may be more appropriate to use an initial sampling rate
of 16 kHz and to process this sample stream with a filtering and
decimating algorithm to achieve a 4 kHz bandlimited signal at
an 8 kHz rate. Figure 23 details the initial 16 kHz sampled tone.
Figure 24 details the spectrum of the final 8 kHz sampled fil-
tered tone.
Figure 24. FFT (ADC 8 kHz Filtered and Decimated from
16 kHz)
–100
–120
–140
–100
–120
–140
–20
–40
–60
–80
–20
–40
–60
–80
Figure 23. FFT (ADC 16 kHz Direct Sampling)
0
0
0
0
1000
500
2000
1000
S
1500
3000
/2) which continues to roll off above
FREQUENCY – Hz
FREQUENCY – Hz
4000
2000
5000
2500
6000
3000
7000
3500
8000
4000
–28–
Encoder Group Delay
When programmed for high sampling rates, the AD73322 offers
a very low level of group delay, which is given by the following
relationship:
where:
If final filtering is implemented in the DSP, the final filter’s
group delay must be taken into account when calculating overall
group delay.
Decoder Section
The decoder section updates (samples) at the same rate as the
encoder section. This rate is programmable as 64 kHz, 32 kHz,
16 kHz or 8 kHz (from a 16.384 MHz MCLK). The decoder
section represents a reverse of the process that was described in
the encoder section. In the case of the decoder section, signals
are applied in the form of samples at an initial low rate. This
sample rate is then increased to the final digital sigma-delta
modulator rate of DMCLK/8 by interpolating new samples
between the original samples. The interpolating filter also has the
action of canceling images due to the interpolation process using
spectral nulls that exist at integer multiples of the initial sam-
pling rate. Figure 25 shows the spectral response of the decoder
section sampling at 64 kHz. Again, its sigma-delta modulator
shapes the noise so it is reduced in the voice bandwidth dc–
4 kHz. For improved voiceband SNR, the user can implement
an initial anti-imaging filter, preceded by 8 kHz to 64 kHz inter-
polation, in the DSP.
Order is the order of the decimator (= 3),
M is the decimation factor (= 32 @ 64 kHz, = 64 @ 32 kHz,
= 128 @ 16 kHz , = 256 @ 8 kHz) and
T
on DMCLK = 16.384 MHz) => Group Delay (Decimator @
64 kHz) = 3
DEC
Group Delay (Decimator) = Order
–100
is the decimation sample interval (= 1/2.048e6) (based
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
Figure 25. FFT (DAC 64 kHz Sampling)
0.5
(32 – 1)/2
1.0
FREQUENCY – Hz
(1/2.048e6) = 22.7 s
1.5
2.0
((M – 1)/2)
2.5
3.0
T
10
DEC
3.5
REV. B
4