CS5381-KZZ Cirrus Logic Inc, CS5381-KZZ Datasheet

IC ADC AUD 120DB 192KHZ 24-TSSOP

CS5381-KZZ

Manufacturer Part Number
CS5381-KZZ
Description
IC ADC AUD 120DB 192KHZ 24-TSSOP
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS5381-KZZ

Package / Case
24-TSSOP
Number Of Converters
2
Number Of Bits
24
Sampling Rate (per Second)
216k
Data Interface
Serial
Power Dissipation (max)
445mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Conversion Rate
192 KSPS
Resolution
24 bit
Number Of Adc Inputs
2
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 10 C
Mounting Style
SMD/SMT
Power Consumption
260 mW
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1592 - REFERENCE DESIGN CS5381 AUD ADC598-1008 - BOARD EVAL FOR CS5381 192KHZ ADC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1092-5

Available stocks

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Price
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CS5381-KZZ
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ATMEL
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Part Number:
CS5381-KZZR
0
Features
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!
!
!
!
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!
!
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Differential
Differential
Inputs
Inputs
Advanced Multi-bit Delta-Sigma Architecture
24-bit Conversion
120 dB Dynamic Range
-110 dB THD+N
Supports All Audio Sample Rates Including
192 kHz
260 mW Power Consumption
High-Pass Filter or DC Offset Calibration
Supports Logic Levels between 5 and 2.5 V
Differential Analog Architecture
Low-Latency Digital Filtering
Overflow Detection
Pin-Compatible with the CS5361
http://www.cirrus.com
120 dB, 192 kHz, Multi-Bit Audio A/D Converter
Switch-Cap
Analog Supply
Internal Voltage
Switch-Cap
Reference
ADC
ADC
5 V
Copyright © Cirrus Logic, Inc. 2005
Digital Supply
3.3 V to 5 V
(All Rights Reserved)
Digital
Filters
Digital
Filters
General Description
The CS5381 is a complete analog-to-digital converter
for digital audio systems. It performs sampling, analog-
to-digital conversion, and anti-alias filtering - generating
24-bit values for both left and right inputs in serial form
at sample rates up to 216 kHz per channel.
The CS5381 uses a 5th-order, multi-bit delta-sigma
modulator followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
The ADC uses a differential architecture which provides
excellent noise rejection.
The CS5381 is available in 24-pin TSSOP and SOIC
packages for Commercial grade (-10° to +70° C). The
CDB5381 Customer Demonstration board is also avail-
able
suggestions. Please refer to the
on page
The CS5381 is ideal for audio systems requiring wide
dynamic range, negligible distortion, and low noise -
such as A/V receivers, DVD-R, CD-R, digital mixing
consoles, and effects processors.
for
22.
device
Interface Supply
2.5 V to 5 V
evaluation
“Ordering Information”
and
CS5381
implementation
Reset
Mode
Configuration
PCM Serial
Audio Output
HPF
OVFL
DS563F2
JULY '05

Related parts for CS5381-KZZ

CS5381-KZZ Summary of contents

Page 1

... CDB5381 Customer Demonstration board is also avail- able for device suggestions. Please refer to the on page 22. The CS5381 is ideal for audio systems requiring wide dynamic range, negligible distortion, and low noise - such as A/V receivers, DVD-R, CD-R, digital mixing consoles, and effects processors. Digital Supply Interface Supply 3 ...

Page 2

... TABLE OF CONTENTS 1. PIN DESCRIPTIONS ............................................................................................................................... 4 2. CHARACTERISTICS AND SPECIFICATIONS....................................................................................... 5 SPECIFIED OPERATING CONDITIONS .................................................................................................... 5 ABSOLUTE MAXIMUM RATINGS............................................................................................................... 5 ANALOG CHARACTERISTICS (CS5381-KSZ/-KZZ).................................................................................. 6 DIGITAL FILTER CHARACTERISTICS....................................................................................................... 7 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT .................................................................... 10 DC ELECTRICAL CHARACTERISTICS.................................................................................................... 13 DIGITAL CHARACTERISTICS .................................................................................................................. 13 THERMAL CHARACTERISTICS .............................................................................................................. 13 TYPICAL CONNECTION DIAGRAM ......................................................................................................... 14 3. APPLICATIONS .................................................................................................................................... 15 3.1 Operational Mode/Sample Rate Range Select.............................................................................. 15 3 ...

Page 3

... Figure 21. OVFL Output Timing, Left-Justified Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 22. Typical Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 23. CS5381 Master Mode Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 24. Recommended Analog Input Buffer Figure 25. CS5381 THD + N versus Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 LIST OF TABLES Table 1. CS5381 Mode Control Table 2. CS5381 Common Master Clock Frequencies Table 3. CS5381 Slave Mode Clock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DS563F2 CS5381 3 ...

Page 4

... Reference Ground (Input) - Ground reference for the internal sampling circuits. REF_GND 24 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. FILT+ 4 RST 1 24 FILT+ M REFGND LRCK SCLK 4 21 AINR+ MCLK 5 20 AINR GND 7 18 GND AINL- SDOUT 9 16 AINL+ MDIV 10 15 OVFL HPF I²S/ CS5381 DS563F2 ...

Page 5

... Positive Digital VD 3.1 Positive Logic VL 2.37 T -10 A (Note 1) Symbol Analog VA Logic VL Digital VD I (Note 2) in (Note 3) V GND-0.7 IN (Note 3) V IND stg CS5381 Typ Max Units 5 5.25 V °C - +70 Min Typ Max Units -0.3 - +6.0 V -0.3 - +6.0 V -0.3 - +6.0 V ...

Page 6

... ANALOG CHARACTERISTICS (CS5381-KSZ/-KZZ) Test conditions (unless otherwise specified): Input test signal kHz sine wave; measurement bandwidth kHz. Parameter Single-Speed Mode Dynamic Range Total Harmonic Distortion + Noise Double-Speed Mode Dynamic Range 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise 40 kHz bandwidth Quad-Speed Mode ...

Page 7

... Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs. DS563F2 Symbol Min Typ (Note -0.1 - (Note 6) 0. 12/Fs gd (Note -0.1 - (Note 6) 0. 9/Fs gd (Note -0.1 - (Note 6) 0. (Note 7) 20 (Note /Fs CS5381 Max Unit 0.47 Fs 0.035 0.45 Fs 0.035 0.24 Fs 0.035 Deg ...

Page 8

... Figure 6. Double-Speed Mode Transition Band CS5381 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 Frequency (normalized to Fs) 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 Frequency (normalized to Fs) ...

Page 9

... Figure 12. Quad-Speed Mode Passband Ripple CS5381 0.15 0.20 0.25 0.30 0.35 0.40 0.45 Frequency (normalized to Fs) 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 Frequency (normalized to Fs) 0 ...

Page 10

... Quad-Speed Mode Fs t 16/f setup t 1/f hold Fs = 48, 96, 192 kHz t clkw t mslr t sdo Fs t sclkw t stp t hld t slrd Fs t sclkw t stp t hld t slrd Fs t sclkw t stp t hld t slrd CS5381 Min Typ Max Unit 108 100 - 216 - - sclk - - sclk - 740 - - 680 - 36 - 1953 - ...

Page 11

... MSB-3 SDOUT Figure 14. Slave Mode, Left-Justified SAI LRCK input SCLK input t sdo SDOUT MSB-1 MSB-2 MSB-3 Figure 16. Slave Mode, I²S SAI t setup Figure 17. OVFL Output Timing CS5381 t slrd t sclkh t sclkl t stp t hld MSB MSB-1 t slrd t sclkh t sclkl t stp t hld MSB t hold ...

Page 12

... OVFL on Left Chan OVFL Figure 21. OVFL Output Timing, Left-Justified Format Figure 18. Left-Justified Serial Audio Interface Figure 19. I²S Serial Audio Interface Left Channel Frame OVFL on Right Chan Figure 20. OVFL Output Timing, I²S Format CS5381 Right Channel Right Channel Right Channel Frame DS563F2 ...

Page 13

... I A VL, VL, VL, VA, VL (Power-Down Mode) - (Note 9) PSRR Output Impedance Output Impedance Symbol (% ovfl I in Symbol Min θ JA-TM θ JA-SM θ JA-TS θ JA-SS CS5381 Typ Max - 100 - - 100 - - 360 445 - 260 307 - 0.01 - Min Typ Max ...

Page 14

... I S/LJ M/S HPF CS5381 M0 M1 A/D CONVERTER MDIV SDOUT LRCK SCLK MCLK GND Figure 22. Typical Connection Diagram CS5381 +5Vto 2 µ Power Down and Mode Settings Audio Data Processor Timing Logic and Clock * Resistor may only be used derived from VA. If used, do not drive any other logic from VD ...

Page 15

... APPLICATIONS 3.1 Operational Mode/Sample Rate Range Select The output sample rate, Fs, can be adjusted from 2 kHz to 216 kHz. The CS5381 must be set to the proper speed mode via the mode pins, M1 and M0. Refer to M1 (Pin 14) M0 (Pin 13 3.2 System Clocking The device supports operation in either Master Mode, where the left/right and serial clocks are synchronous- ly generated on-chip, or Slave Mode, which requires external generation of the left/right and serial clocks ...

Page 16

... Table 2. CS5381 Common Master Clock Frequencies 3.2.2 Slave Mode LRCK and SCLK operate as inputs in Slave mode recommended that the left/right clock be synchro- nously derived from the master clock and must be equal to Fs also recommended that the serial clock be synchronously derived from the master clock and be equal to 64x Fs to maximize system performance ...

Page 17

... High-Pass Filter and DC Offset Calibration The operational amplifiers in the input circuitry driving the CS5381 may generate a small DC offset into the A/D converter. The CS5381 includes a high-pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding “clicks” when switching between devices in a multi- channel system ...

Page 18

... MCLK and LRCK must be the same for all of the CS5381’s in the system. If only one master clock source is needed, one solution is to place one CS5381 in Master mode, and slave all of the other CS5381’s to the one master. If multiple master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS5381 reset with the falling edge of MCLK ...

Page 19

... Capacitor Size on the Reference Pin (FILT+) The CS5381 requires an external capacitance on the internal reference voltage pin, FILT+. The size of this decoupling capacitor will affect the low frequency distortion performance as shown in capacitor values used to optimize low frequency distortion performance. The THD+N curves in were measured with VA=VD=VL Single-Speed Master Mode with a full-scale sinewave input ...

Page 20

... CS5381 MILLIMETERS MAX 2.65 0.30 0.51 0.32 15.60 7.60 1.52 10.65 1.27 8° DS563F2 ∝ ...

Page 21

... JEDEC #: MO-153 Controlling Dimension is Millimeters. CS5381 1 E1 END VIEW L MILLIMETERS NOTE NOM MAX -- 1.10 -- 0.15 0.90 0.95 0.245 0.30 2,3 7.80 7.90 6.40 6.50 4.40 4 ...

Page 22

... Audio A/D Converter CDB5381 CS5381 Evaluation Board 22 Package Pb-Free Grade 24-TSSOP Yes Commercial -10° to +70° C 24-SOIC Yes Commercial -10° to +70° CS5381 Temp Container Order # Range Bulk CS5381-KZZ Tape & Reel CS5381-KZZR Bulk CS5381-KSZ Tape & Reel CS5381-KSZR - - CDB5381 DS563F2 ...

Page 23

... The deviation from the nominal full-scale analog input for a full-scale digital output. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. DS563F2 CS5381 23 ...

Page 24

... AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. 24 Changes ) specification from mA www.cirrus.com CS5381 DS563F2 ...

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