AD9246BCPZ-125 Analog Devices Inc, AD9246BCPZ-125 Datasheet - Page 20

• Manufacturer Part Number: AD9246BCPZ-125
• Description: IC ADC 14BIT 125MSPS 48-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9246BCPZ-125

• Data Interface: Serial, SPI™
• Design Resources: Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002) Driving AD9233/46/54 ADCs in AC-Coupled Baseband Appls (CN0051)
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Number Of Converters: 3
• Power Dissipation (max): 425mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN, CSP Exposed Pad
• Resolution (bits): 14bit
• Sampling Rate: 125MSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 1.7V To 1.9V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9246-125EBZ - BOARD EVAL FOR 125MSPS AD9246AD9246-105EBZ - BOARD EVAL FOR 105MSPS AD9246
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9246
The DCS can be enabled or disabled by setting the SDIO/DCS
pin when operating in the external pin mode (see Table 10), or
via the SPI, as described in Table 13.
Table 10. Mode Selection (External Pin Mode)
Voltage at Pin
AGND
AVDD
JITTER CONSIDERATIONS
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (f
In the equation, the rms aperture jitter represents the root mean
square of all jitter sources, which include the clock input, analog
input signal, and ADC aperture jitter specification. IF under-
sampling applications are particularly sensitive to jitter, as
illustrated in Figure 51.
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9246. Power supplies
for clock drivers should be separated from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
The power supplies should also not be shared with analog input
circuits, such as buffers, to avoid the clock modulating onto the
input signal or vice versa. Low jitter, crystal-controlled oscillators
make the best clock sources. If the clock is generated from
another type of source (by gating, dividing, or other methods),
it should be retimed by the original clock at the last step.
Refer to Application Notes AN-501, Aperture Uncertainty and
ADC System Performance, and AN-756, Sampled Systems and
the Effects of Clock Phase Noise and Jitter, for more in-depth
information about jitter performance as it relates to ADCs.
SNR = −20 log (2π × f
75
70
65
60
55
50
45
40
1
IN
PERFORMANCE
Figure 51. SNR vs. Input Frequency and Jitter
) due to jitter (t
MEASURED
SCLK/DFS
Binary (default)
Twos complement
INPUT FREQUENCY (MHz)
10
IN
× t
J
) is calculated as follows:
J
)
100
SDIO/DCS
DCS disabled
DCS enabled
(default)
0.05ps
0.20ps
0.5ps
1.0ps
1.50ps
2.00ps
2.50ps
3.00ps
1000
Rev. A | Page 20 of 44
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 52 and Figure 53, the power dissipated by
the AD9246 is proportional to its sample rate. The digital power
dissipation is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current (I
where N is the number of output bits, 14 in the case of the
AD9246.
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency, f
established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal. Reducing the capacitive load
presented to the output drivers can minimize digital power
consumption. The data in Figure 52 and Figure 53 was taken
under the same operating conditions as the data for the Typical
Performance Characteristics section, with a 5 pF load on each
output driver.
Figure 52. AD9246-125 Power and Current vs. Clock Frequency f
Figure 53. AD9246-105 Power and Current vs. Clock Frequency f
475
450
425
400
375
350
325
410
390
370
350
330
310
290
270
250
I
DRVDD
0
0
DRVDD
=
V
) can be calculated as:
IAVDD
IAVDD
DRVDD
TOTAL POWER
25
25
TOTAL POWER
CLK
CLOCK FREQUENCY (MSPS)
CLOCK FREQUENCY (MSPS)
×
/2. In practice, the DRVDD current is
C
LOAD
50
50
×
IDRVDD
f
IDRVDD
CLK
2
75
×
N
75
100
100
1
IN
IN
25
= 30 MHz
= 30 MHz
250
200
150
100
50
0
200
180
160
140
120
100
80
60
40
20
0