MAX1379ATP+ Maxim Integrated Products, MAX1379ATP+ Datasheet - Page 20

• Manufacturer Part Number: MAX1379ATP+
• Description: IC ADC 12BIT 1.25MSPS DL 20-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX1379ATP+

• Number Of Bits: 12
• Sampling Rate (per Second): 1.25M
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 40mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-WQFN, Exposed Pad
• Number Of Adc Inputs: 2
• Architecture: SAR
• Conversion Rate: 1.25 MSPs
• Resolution: 10 bit
• Interface Type: Dual Serial
• Voltage Reference: Internal 4.096 V or External
• Supply Voltage (max): 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
Drive CNVST low and allow at least 14 SCLK cycles to
elapse before driving CNVST high to exit partial or full
power-down mode. When exiting partial power-down
mode, conversions can begin immediately without hav-
ing to wait for the reference to wake-up. When exiting
full power-down mode, allow at least 2ms recovery time
after exiting to ensure that the internal reference has
settled.
In partial or full power-down mode, maintain idle SCLK
low or high to minimize power.
Figure 11. Partial Power-Down Timing Sequence
Figure 12. Full Power-Down Mode Timing Sequence
20
DOUT_
MODE
______________________________________________________________________________________
CNVST
REF
DOUT_
SCLK
CNVST
MODE
SCLK
REF
Exiting Partial and Full Power-Down Modes
0
1ST SCLK RISING EDGE
1
0
1ST SCLK RISING EDGE
0
0
0
NORMAL
3
0
D11
NORMAL
D11
D10
D10
D9
1ST SCLK RISING EDGE
D9
D8
D8
D7
ENABLED
PPD WINDOW
D7
ENABLED
The MAX1377/MAX1379/MAX1383 are compatible with
all four modes programmed with the CPHA and CPOL
bits in the SPI or MICROWIRE control register.
Conversion begins with a CNVST falling edge. DOUT_
goes low, indicating a conversion is in progress. Two
consecutive 8-bit reads are required to get the full 12
bits from the ADC. DOUT_ transitions on the rising edge
of SCLK. DOUT_ is guaranteed to be valid t
the rising edge of SCLK and remains valid until t
after the next SCLK rising edge (see Figure 13).
9
CNVST MUST GO HIGH AFTER THE 3RD
BUT BEFORE THE 14TH
SCLK RISING EDGE
DOUT_ GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH
0
EXECUTE PARTIAL POWER-DOWN SEQUENCE TWICE
DOUT_ ENTERS THREE-STATE ONCE CNVST GOES HIGH
0
0
Applications Information
PARTIAL POWER-DOWN
0
PPD
0
14
SPI and MICROWIRE
0
0
0
DOUT
DISABLED
FPD
DHOLD
after