MAX146BEAP+ Maxim Integrated Products, MAX146BEAP+ Datasheet - Page 15

• Manufacturer Part Number: MAX146BEAP+
• Description: IC ADC LP 12-BIT 133KSPS 20-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX146BEAP+

• Number Of Bits: 12
• Sampling Rate (per Second): 133k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 640mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Number Of Adc Inputs: 8
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 12 bit
• Interface Type: Serial
• Voltage Reference: Internal 2.5 V or External
• Supply Voltage (max): 3.3 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The falling edge of CS does not start a conversion.
The first logic high clocked into DIN is interpreted as a
start bit and defines the first bit of the control byte. A
conversion starts on SCLK’s falling edge, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as follows:
If CS is toggled before the current conversion is com-
plete, the next high bit clocked into DIN is recognized as
a start bit; the current conversion is terminated, and a
new one is started.
The fastest the MAX146/MAX147 can run with CS held
low between conversions is 15 clocks per conversion.
Figure 11a shows the serial-interface timing necessary to
perform a conversion every 15 SCLK cycles in external
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
DOUT
SCLK
DIN
SSTRB
CS
The first high bit clocked into DIN with CS low any
time the converter is idle; e.g., after V
The first high bit clocked into DIN after bit 5 of a con-
version in progress is clocked onto the DOUT pin.
DOUT
SCLK
DIN
CS
S
1
S
1
CONTROL BYTE 0
______________________________________________________________________________________
CONTROL BYTE 0
OR
8
8
Data Framing
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
DD
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
is applied.
+2.7V, Low-Power, 8-Channel,
CONVERSION RESULT 0
CONVERSION RESULT 0
15
S
1
16
clock mode. If CS is tied low and SCLK is continuous,
guarantee a start bit by first clocking in 16 zeros.
Most microcontrollers (µCs) require that conversions
occur in multiples of 8 SCLK clocks; 16 clocks per con-
version is typically the fastest that a µC can drive the
MAX146/MAX147. Figure 11b shows the serial-
interface timing necessary to perform a conversion every
16 SCLK cycles in external clock mode.
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX146/MAX147 in internal clock mode, ready to con-
vert with SSTRB = high. After the power supplies stabi-
lize, the internal reset time is 10µs, and no conversions
should be performed during this phase. SSTRB is high
on power-up and, if CS is low, the first logical 1 on DIN
is interpreted as a start bit. Until a conversion takes
place, DOUT shifts out zeros. (Also see Table 4.)
CONTROL BYTE 1
S
1
CONTROL BYTE 1
Serial 12-Bit ADCs
8
Applications Information
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
8
CONVERSION RESULT 1
15
CONVERSION RESULT 1
B11 B10 B9 B8
Power-On Reset
S
1
CONTROL BYTE 2
16
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