MAX146ACAP Maxim Integrated Products, MAX146ACAP Datasheet
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MAX146ACAP
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MAX146ACAP Summary of contents
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... Software-Configurable Unipolar or Bipolar Inputs o 20-Pin DIP/SSOP Packages PART TEMP RANGE MAX146ACPP 0°C to +70°C MAX146BCPP 0°C to +70°C MAX146ACAP 0°C to +70°C MAX146BCAP 0°C to +70°C MAX146BC/D 0°C to +70°C Ordering Information continued at end of data sheet. *Dice are specified at T Typical Operating Circuit ...
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Low-Power, 8-Channel, Serial 12-Bit ADCs ABSOLUTE MAXIMUM RATINGS V to AGND, DGND................................................. -0. AGND to DGND ...................................................... -0.3V to 0.3V CH0–CH7, COM to AGND, DGND ............ -0. VREF, REFADJ to AGND ........................... -0.3V to ...
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ELECTRICAL CHARACTERISTICS (continued +2.7V to +3.6V (MAX146 clocks/conversion cycle (133ksps); MAX146—4.7µF capacitor at VREF pin; MAX147—external reference, VREF = 2.500 V applied to VREF pin unless otherwise noted.) A ...
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Low-Power, 8-Channel, Serial 12-Bit ADCs ELECTRICAL CHARACTERISTICS (continued +2.7V to +3.6V (MAX146 +2.7V to +5.25V (MAX147); COM = clocks/conversion cycle (133ksps); MAX146—4.7µF capacitor at VREF pin; MAX147—external reference, VREF = 2.500 ...
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TIMING CHARACTERISTICS (V = +2.7V to +3.6V (MAX146 PARAMETER SYMBOL Acquisition Time DIN to SCLK Setup DIN to SCLK Hold SCLK Fall to Output Data Valid CS Fall to Output Enable CS Rise to Output Disable CS ...
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Low-Power, 8-Channel, Serial 12-Bit ADCs (V = 3.0V, VREF = 2.5V 2.0MHz SCLK SUPPLY CURRENT vs. SUPPLY VOLTAGE 2.00 = ∞ CODE = 101010100000 C = 50pF LOAD 1.75 1.50 MAX146 1.25 1.00 ...
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VREF = 2.5V 2.0MHz SCLK OFFSET vs. SUPPLY VOLTAGE 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 2.25 2.75 3.25 3.75 4.25 4.75 V (V) DD OFFSET vs. TEMPERATURE 0.50 ...
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Low-Power, 8-Channel, Serial 12-Bit ADCs ______________________________________________________________Pin Description PIN NAME 1–8 CH0–CH7 Sampling Analog Inputs Ground reference for analog inputs. COM sets zero-code voltage in single-ended mode. Must be 9 COM stable to ±0.5LSB. Three-Level Shutdown Input. Pulling SHDN low ...
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Description The MAX146/MAX147 analog-to-digital converters (ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 12-bit digital output. A flexible ser- ial interface provides easy interface to microprocessors (µPs). Figure 3 ...
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Low-Power, 8-Channel, Serial 12-Bit ADCs The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal’s source impedance is high, the acquisition time lengthens, ...
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Table 1. Control-Byte Format BIT 7 BIT 6 BIT 5 (MSB) START SEL2 SEL1 BIT NAME DESCRIPTION The first logic “1” bit after CS goes low defines the beginning of the control byte. 7(MSB) START 6 SEL2 These three bits ...
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Low-Power, 8-Channel, Serial 12-Bit ADCs How to Start a Conversion Start a conversion by clocking a control byte into DIN. With CS low, each rising edge on SCLK clocks a bit from DIN into the MAX146/MAX147’s internal shift register. ...
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CS t CSS t CSH SCLK DIN t DV DOUT Figure 7. Detailed Serial-Interface Timing CS t SDV SSTRB SCLK • Figure 8. External Clock Mode SSTRB Detailed Timing In external clock mode, the external clock ...
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Low-Power, 8-Channel, Serial 12-Bit ADCs processor’s convenience, at any clock rate from 0MHz to 2MHz. SSTRB goes low at the start of the conversion and then goes high when the conversion is complete. SSTRB is low for a maximum ...
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The falling edge of CS does not start a conversion. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. A conversion starts on SCLK’s falling edge, after ...
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Low-Power, 8-Channel, Serial 12-Bit ADCs Reference-Buffer Compensation In addition to its shutdown function, SHDN selects inter- nal or external compensation. The compensation affects both power-up time and maximum conversion speed. The100kHz minimum clock rate is limited by droop on ...
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CLOCK MODE SHDN SETS EXTERNAL CLOCK MODE DIN DOUT 12 DATA BITS POWERED UP MODE Figure 12a. Timing Diagram Power-Down Modes, External Clock CLOCK MODE SETS INTERNAL CLOCK MODE DIN S X ...
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Low-Power, 8-Channel, Serial 12-Bit ADCs Power-Down Sequencing The MAX146/MAX147 auto power-down modes can save considerable power when operating at less than maximum sample rates. Figures 13, 14a, and 14b show the average supply current as a function of the ...
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DIN FULLPD 1.21V REFADJ 0V 2.50V VREF 0V Figure 15. MAX146 FULLPD/FASTPD Power-Up Sequence Lowest Power at Higher Throughputs Figure 14b shows the power consumption with external-reference compensation in fast power-down, with one and eight channels ...
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Low-Power, 8-Channel, Serial 12-Bit ADCs VREF, the DC input resistance is a minimum of 18kΩ. During conversion, an external reference at VREF must deliver up to 350µA DC load current and have 10Ω or less output impedance. If the ...
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OUTPUT CODE FS = VREF + COM 011 . . . 111 2 011 . . . 110 ZS = COM -VREF - COM 2 000 . . . 010 VREF 000 . . . 001 1LSB = ...
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Low-Power, 8-Channel, Serial 12-Bit ADCs 1 CH0 2 CH1 CH2 3 4 ANALOG CH3 MAX146 INPUTS MAX147 5 CH4 6 CH5 7 CH6 8 CH7 9 COM 10 SHDN Figure 20. MAX146/MAX147 QSPI Connections, External Reference CS XF SCLK ...
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CS SCLK DIN START SEL2 SEL1 SSTRB DOUT Figure 22. TMS320 Serial-Interface Timing Diagram Ordering Information (continued) PART TEMP RANGE PIN-PACKAGE MAX146AEPP -40°C to +85°C 20 Plastic DIP MAX146BEPP -40°C to +85°C 20 Plastic DIP MAX146AEAP -40°C to +85°C 20 ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 © 2001 Maxim Integrated Products ...