MAX1202ACAP+ Maxim Integrated Products, MAX1202ACAP+ Datasheet - Page 13

• Manufacturer Part Number: MAX1202ACAP+
• Description: IC ADC 12BIT 8CH 20-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1202ACAP+

• Number Of Bits: 12
• Sampling Rate (per Second): 133k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 640mW
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion padded with
one leading zero and three trailing zeros. The total conver-
sion time is a function of the serial-clock frequency and
the amount of idle time between 8-bit transfers. To avoid
excessive T/H droop, make sure that the total conversion
time does not exceed 120µs.
Figure 6. 24-Bit External Clock Mode Conversion Timing (MICROWIRE and SPI Compatible)
1) Set up the control byte for external clock mode and
2) Use a general-purpose I/O line on the CPU to pull
3) Transmit TB1 and simultaneously receive a byte
4) Transmit a byte of all zeros ($00 hex) and simulta-
5) Transmit a byte of all zeros ($00 hex) and simulta-
6) Pull CS on the MAX1202/MAX1203 high.
SSTRB
ADC STATE
DOUT
SCLK
DIN
CS
call it TB1. TB1’s format should be: 1XXXXX11 binary,
where the Xs denote the particular channel and
conversion mode selected.
CS on the MAX1202/MAX1203 low.
and call it RB1. Ignore RB1.
neously receive byte RB2.
neously receive byte RB3.
START
1
SEL2 SEL1 SEL0
IDLE
______________________________________________________________________________________
RB1
4
UNI/
BIP
Simple Software Interface
SGL/
DIF
(SCLK = 2MHz)
ACQUISITION
1.5µs
t
ACQ
5V, 8-Channel, Serial, 12-Bit ADCs
PD1
PD0
8
MSB
B11
B10
with 3V Digital Interface
B9
12
RB2
B8
In unipolar-input mode, the output is straight binary
(Figure 15); for bipolar inputs, the output is two’s-
complement (Figure 16). Data is clocked out at SCLK’s
falling edge in MSB-first format. The digital output logic
level is adjusted with the VL pin. This allows DOUT and
SSTRB to interface with 3V logic without the risk of
overdrive. The MAX1202/MAX1203’s digital inputs are
designed to be compatible with 5V CMOS logic as well
as 3V logic.
The MAX1202/MAX1203 can use either an external ser-
ial clock or the internal clock to perform the successive-
approximation conversion. In both clock modes, the
external clock shifts data in and out of the MAX1202/
MAX1203. The T/H acquires the input signal as the last
three bits of the control byte are clocked into DIN. Bits
PD1 and PD0 of the control byte program the clock
mode. Figures 7–10 show the timing characteristics
common to both modes.
In external clock mode, the external clock not only shifts
data in and out, but it also drives the A/D conversion
steps. SSTRB pulses high for one clock period after the
last bit of the control byte. Successive-approximation bit
decisions are made and appear at DOUT on each of the
next 12 SCLK falling edges (Figure 6). SSTRB and
DOUT go into a high-impedance state when CS goes
high; after the next CS falling edge, SSTRB outputs a
logic low. Figure 8 shows SSTRB timing in external clock
mode.
CONVERSION
B7
B6
Internal and External Clock Modes
B5
16
B4
B3
B2
B1
20
RB3
LSB
B0
FILLED WITH
ZEROS
External Clock
IDLE
Digital Output
24
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