MAX1134BEAP+ Maxim Integrated Products, MAX1134BEAP+ Datasheet - Page 9

• Manufacturer Part Number: MAX1134BEAP+
• Description: IC ADC 16BIT 150KSPS 20-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1134BEAP+

• Number Of Bits: 16
• Sampling Rate (per Second): 150k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 26.4mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Conversion Rate: 150 KSPs
• Resolution: 16 bit
• Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Snr: 84 dB
• Voltage Reference: 2.048 V
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Maximum Power Dissipation: 640 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 3.3 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

range is 0 to +2.048V (unipolar) or ±2.048V (bipolar).
Unipolar and bipolar mode selection is configured with
bit 6 of the serial control byte (Table 1).
Figure 1 shows the equivalent input circuit of the
MAX1134/MAX1135. The resistor network on the analog
input provides ±16.5V fault protection. This circuit limits
the current going into or out of the pin to less than 2mA.
The overvoltage protection is active even if the device
is in a power-down mode, or if AV
The digital interface pins consist of SHDN, RST,
SSTRB, DOUT, SCLK, DIN, and CS. Bringing SHDN low
places the MAX1134/MAX1135 in its 1.2µA shutdown
mode. A logic low on RST halts the MAX1134/MAX1135
operation and returns the part to its power-on-reset
state.
In external clock mode, SSTRB is low and pulses high
for one clock cycle at the start of conversion. In internal
clock mode, SSTRB goes low at the start of the conver-
sion, and goes high to indicate that the conversion is
finished.
The DIN input accepts control byte data, which is
clocked in on each rising edge of SCLK. After CS goes
Figure 2. Short Acquisition Mode (24 Clock Cycles) External Clock
Table 2. User-Programmable Outputs
OUTPUT PIN
SSTRB
DOUT
SCLK
DIN
STATE
P2
P1
P0
CS
A/D
START
IDLE
16-Bit ADCs, 150ksps, 3.3V Single Supply
1
THROUGH CONTROL
UNI/
_______________________________________________________________________________________
BIP
PROGRAMMED
INT/
EXT
ACQUISITION
BYTE
t
Bit 2
Bit 1
Bit 0
ACQ
M1
4
M0
DD
Digital Interface
P2
= 0.
P1
POWER-ON OR
RST DEFAULT
P0
8
MSB
B15
0
0
0
B14
B13
B12
User-programmable outputs follow the state of the control
byte’s 3 LSBs, and are updated simultaneously when a new
control byte is written. Outputs are push-pull. In hardware and
software shutdown, these outputs are unchanged and remain
low impedance.
low or after a conversion or calibration completes, the
first logic 1 clocked into DIN is interpreted as the
START bit, the MSB of the 8-bit control byte.
The SCLK input is the serial-data-transfer clock, which
clocks data in and out of the MAX1134/MAX1135.
SCLK also drives the ADC conversion steps in external
clock mode (see the Internal and External Clock Modes
section).
DOUT is the serial output of the conversion result.
DOUT is updated on the falling edge of SCLK. DOUT is
high impedance when CS is high.
CS must be low for the MAX1134/MAX1135 to accept a
control byte. The serial interface is disabled when CS is
high.
The MAX1134/MAX1135 have three user-program-
mable outputs: P0, P1, and P2. The power-on default
state for the programmable outputs is zero. These are
push-pull CMOS outputs suitable for driving a multi-
plexer, a PGA, or other signal preconditioning circuitry.
Bits 0, 1, and 2 of the control byte control the user-pro-
grammable outputs (Tables 1, 2).
12
B11
CONVERSION
B10
B9
15
User-Programmable Outputs
B4
DESCRIPTION
B3
21
B2
B1
LSB
B0
24
FILLED WITH
ZEROS
IDLE
9