CS5525-ASZ Cirrus Logic Inc, CS5525-ASZ Datasheet - Page 24

• Manufacturer Part Number: CS5525-ASZ
• Description: IC ADC 16BIT W/4BIT LATCH 20SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5525-ASZ

• Number Of Converters: 1
• Package / Case: 20-SSOP
• Number Of Bits: 16
• Data Interface: Serial
• Power Dissipation (max): 12.7mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 1
• Architecture: Delta-Sigma
• Conversion Rate: 3.76 SPs to 616 SPs
• Resolution: 16 bit
• Input Type: Voltage
• Interface Type: Serial (3-Wire)
• Voltage Reference: 2.5 V
• Supply Voltage (max): 5 V
• Supply Voltage (min): 25 mV
• Maximum Power Dissipation: 500 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 25 mV to 5 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1013 - EVAL BOARD FOR CS5525
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1107-5

PIN DESCRIPTIONS
Clock Generator
XIN; XOUT - Crystal In; Crystal Out, Pins 9, 10.
Control Pins and Serial Data I/O
CS - Chip Select, Pin 18.
SDI - Serial Data Input, Pin 17.
SDO - Serial Data Output, Pin 14.
SCLK - Serial Clock Input, Pin 11.
A0, A1, A2, A3 - Logic Outputs, Pin 6, 7, 15, 16.
24
DIFFERENTIAL ANALOG INPUT
DIFFERENTIAL ANALOG INPUT
A gate inside the chip is connected to these pins and can be used with a crystal to provide the
master clock for the device. Alternatively, an external (CMOS compatible) clock can be
supplied into the XIN pin to provide the master clock for the device.
When active low, the port will recognize SCLK. When high the SDO pin will output a high
impedance state. CS should be changed when SCLK = 0.
SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK.
A clock signal on this pin determines the input/output rate of the data for the SDI/SDO pins
respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin
will recognize clocks only when CS is low.
The logic states of A0-A3 mimic the states of the D20-D23 bits of the configuration register.
Logic Output 0 = AGND, and Logic Output 1 = VA+.
SDO is the serial data output. It will output a high impedance state if CS = 1.
POSITIVE ANALOG POWER
NEGATIVE BIAS VOLTAGE
CHARGE PUMP DRIVE
ANALOG GROUND
LOGIC OUTPUT
LOGIC OUTPUT
CRYSTAL OUT
CRYSTAL IN
AGND
XOUT
AIN+
NBV
CPD
AIN-
VA+
XIN
A0
A1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VREF+ VOLTAGE REFERENCE INPUT
VREF- VOLTAGE REFERENCE INPUT
CS
SDI
A3
A2
SDO
VD+
DGND DIGITAL GROUND
SCLK SERIAL CLOCK INPUT
CHIP SELECT
SERIAL DATA INPUT
LOGIC OUTPUT
LOGIC OUTPUT
SERIAL DATA OUTPUT
POSITIVE DIGITAL POWER
CS5525 CS5526
DS202F5