MAX1228BCEP+ Maxim Integrated Products, MAX1228BCEP+ Datasheet - Page 17
![IC ADC 12-BIT 300KSPS 20-QSOP](/photos/6/61/66144/20-qsop_21-0055_sml.jpg)
MAX1228BCEP+
Manufacturer Part Number
MAX1228BCEP+
Description
IC ADC 12-BIT 300KSPS 20-QSOP
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX1228BEEP.pdf
(23 pages)
Specifications of MAX1228BCEP+
Number Of Bits
12
Sampling Rate (per Second)
300k
Data Interface
MICROWIRE™, QSPI™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
727mW
Voltage Supply Source
Single Supply
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
20-QSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
In clock mode 00, the wake up, acquisition, conversion,
and shutdown sequences are initiated through CNVST
and performed automatically using the internal oscilla-
tor. Results are added to the internal FIFO to be read
out later. See Figure 4 for clock mode 00 timing.
Initiate a scan by setting CNVST low for at least 40ns
before pulling it high again. The MAX1226/MAX1228/
MAX1230 then wake up, scan all requested channels,
store the results in the FIFO, and shut down. After the
scan is complete, EOC is pulled low and the results are
available in the FIFO. Wait until EOC goes low before
pulling CS low to communicate with the serial interface.
EOC stays low until CS or CNVST is pulled low again. A
temperature measurement result, if requested, pre-
cedes all other FIFO results.
Do not initiate a second CNVST before EOC goes low;
otherwise the FIFO can become corrupted.
In clock mode 01, conversions are requested one at a
time using CNVST and performed automatically using the
internal oscillator. See Figure 5 for clock mode 01 timing.
Setting CNVST low begins an acquisition, wakes up the
ADC, and places it in track mode. Hold CNVST low for
at least 1.4µs to complete the acquisition. If internal ref-
Figure 4. Clock Mode 00
Internally Timed Conversions with CNVST
CNVST
SCLK
DOUT
EOC
CS
SET CNVST LOW FOR AT LEAST 40ns TO BEGIN A CONVERSION.
Performing Conversions in Clock Mode 00
Performing Conversions in Clock Mode 01
Externally Timed Acquisitions and
Internally Timed Acquisitions and
______________________________________________________________________________________
Conversions Using CNVST
Temp Sensor, Internal Reference
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
12-Bit 300ksps ADCs with FIFO,
MSB1
erence needs to wake up, an additional 65µs is
required for the internal reference to power up. If a tem-
perature measurement is being requested, reference
power-up and temperature measurement are internally
timed. In this case, hold CNVST low for at least 40ns.
Set CNVST high to begin a conversion. After the con-
version is complete, the ADC shuts down and pulls
EOC low. EOC stays low until CS or CNVST is pulled
low again. Wait until EOC goes low before pulling CS or
CNVST low.
If averaging is turned on, multiple CNVST pulses need
to be performed before a result is written to the FIFO.
Once the proper number of conversions has been per-
formed to generate an averaged FIFO result, as speci-
fied by the averaging register, the scan logic
automatically switches the analog input multiplexer to
the next-requested channel. If a temperature measure-
ment is programmed, it is performed after the first rising
edge of CNVST following the input data byte written to
the conversion register. The result is available on DOUT
once EOC has been pulled low.
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequences are initiated by writing an
input data byte to the conversion register, and are per-
formed automatically using the internal oscillator. This
is the default clock mode upon power-up. See Figure 6
for clock mode 10 timing.
Conversions Using the Serial Interface
Performing Conversions in Clock Mode 10
Internally Timed Acquisitions and
LSB1
MSB2
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