LTC1196-2BCS8 Linear Technology, LTC1196-2BCS8 Datasheet - Page 24

• Manufacturer Part Number: LTC1196-2BCS8
• Description: IC A/DCONV 8BIT 1MHZ SAMPL 8SOIC
• Manufacturer: Linear Technology

Specifications of LTC1196-2BCS8

• Number Of Bits: 8
• Sampling Rate (per Second): 1M
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 50mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

TYPICAL APPLICATIONS
LTC1196/LTC1198
Interfacing the LTC1198 to the TMS320C25 DSP
Figure 15 illustrates the interface between the LTC1198
8-bit data acquisition system and the TMS320C25 digital
signal processor (DSP). The interface, which is optimized
for speed of transfer and minimum processor supervision,
can complete a conversion and shift the data in 4μs with
f
limited by maximum clock frequency of the serial port of
the TMS320C25 which is 5MHz. The supply voltage for
24
CLK
Figure 15. Interfacing the LTC1198 to the TMS320C25 DSP
= 5MHz. The cycle time, 4μs, of each conversion is
TMS320C25
CLKR
CLKX
FSR
FSX
DR
DX
DATA
CLK
CS
B7
B6
B5
B4
B3
B2
B1
B0
70
5MHz CLK
140 210 280
CS
D
D
CLK
IN
OUT
LTC1198
350
1196/98 F15
CH0
CH1
Figure 14. The Timing Diagram
420
490
560
TIME (ns)
630
the LTC1198 in Figure 15 can be 2.7V to 6V with f
5MHz. At 2.7V, f
Recommended Operating Conditions table in the Electrical
Characteristics section for limits over temperature.
Hardware Description
The circuit works as follows: the LTC1198 clock line
controls the A/D conversion rate and the data shift rate.
Data is transferred in a synchronous format over D
D
with that of the LTC1198. The data shift clock lines (CLKR,
CLKX) are inputs only. The data shift clock comes from
an external source. Inverting the shift clock is necessary
because the LTC1198 and the TMS320C25 clock the input
data on opposite edges.
The schematic of Figure 15 is fed by an external clock
source. The signal is fed into the CLK pin of the LTC1198
directly. The signal is inverted with a 74HC04 and then
applied to the data shift clock lines (CLKR, CLKX). The
framing pulse of the TMS320C25 is fed directly to the CS
of the LTC1198. DX and DR are tied directly to D
D
OUT
OUT
700 770
, respectively.
. The serial port of the TMS320C25 is compatible
840 910
CLK
980 1050 1120
= 5MHz will work at 25°C. See the
1196/98 F14
IN
IN
119698fb
CLK
and
and
=