LTC1199CS8 Linear Technology, LTC1199CS8 Datasheet - Page 13

• Manufacturer Part Number: LTC1199CS8
• Description: IC ADC 10BIT 450KHZ W/SD 8-SOIC
• Manufacturer: Linear Technology

Specifications of LTC1199CS8

• Number Of Bits: 10
• Sampling Rate (per Second): 450k
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 25mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
The LTC1197/LTC1197L do not require a configuration
input word and have no D
transfer as shown in the LTC1197/LTC1197L operating
sequence. After CS falls, the second CLK pulse enables
D
on the D
resets the LTC1197/LTC1197L for the next data exchange
and minimizes the supply current if CLK is continuously
running.
INPUT DATA WORD (LTC1199/LTC1199L ONLY)
The LTC1199 4-bit data word is clocked into the D
on the rising edge of the clock after CS goes low and the
start bit has been recognized. Further inputs on the D
are then ignored until the next CS cycle. The input word is
defined as follows:
Start Bit
The first “logical one” clocked into the D
goes low is the start bit. The start bit initiates the data
OUT
. After two null bits, the A/D conversion result is output
D
OUT
CLK
D
CS
IN
OUT
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT ZEROS INDEFINITELY
HI-Z
line in MSB-first format. Bringing CS high
START
START
1
U
t
suCS
SGL/
DIFF
2
SGL/
DIFF
ADDRESS
IN
ODD/
SIGN
U
MUX
pin. A falling CS initiates data
3
(1.5 CLKs)
DUMMY
ODD/
SIGN
t
SMPL
4
W
DUMMY
1197/99 AI01
Figure 2. LTC1199/LTC1199L Operating Sequence
NULL
5
BITS
t
en
IN
input after CS
6
U
B9
IN
7
IN
B8
input
t
CYC
t
dDO
pin
8
(16 CLKs)*
B7
(10.5 CLKs)
9
transfer and all leading zeros that precede this logical one
will be ignored. After the start bit is received the remaining
bits of the input word will be clocked in. Further inputs on
the D
Multiplexer (MUX) Address
The bits of the input word following the start bit assign the
MUX configuration for the requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+” and
“–” signs in the selected row of the following table. In
single-ended mode, all input channels are measured with
respect to GND. Only the + inputs have sample-and-holds.
Signals applied at the – inputs must not change more than
the required accuracy during the conversion.
t
CONV
B6
10
DON’T CARE
IN
B5
pin are then ignored until the next CS cycle.
11
B4
SGL/DIFF
12
Multiplexer Channel Selection
MUX ADDRESS
1
1
0
0
B3
13
ODD/SIGN
LTC1197/LTC1197L
LTC1199/LTC1199L
B2
0
1
0
1
14
B1
CHANNEL #
+
+
–
0
15
B0*
POWER
DOWN
16
+
–
+
1
1197/99 AI02
GND
Hi-Z
–
–
1197/99 F02
1
13