LTC2439-1CGN#TR Linear Technology, LTC2439-1CGN#TR Datasheet - Page 20

• Manufacturer Part Number: LTC2439-1CGN#TR
• Description: IC ADC 16BIT 16CH MCRPWR 28SSOP
• Manufacturer: Linear Technology

Specifications of LTC2439-1CGN#TR

• Number Of Bits: 16
• Sampling Rate (per Second): 6.8
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.150", 3.95mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
LTC2439-1
Digital Signal Levels
The LTC2439-1’s digital interface is easy to use. Its digital
inputs (SDI, F
operation) accept standard TTL/CMOS logic levels and the
internal hysteresis receivers can tolerate edge rates as slow
as 100µs. However, some considerations are required to
take advantage of the accuracy and low supply current of
this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(V
current from the power supply. It should be noted that,
when any one of the digital input signals (SDI, F
SCK in External SCK mode of operation) is within this
range, the power supply current may increase even if the
signal in question is at a valid logic level. For micropower
operation, it is recommended to drive all digital input
signals to full CMOS levels [V
V
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the pins
may severely disturb the analog to digital conversion
process. Undershoot and overshoot can occur because of
the impedance mismatch at the converter pin when the
transition time of an external control signal is less than
twice the propagation delay from the driver to LTC2439-
1. For reference, on a regular FR-4 board, signal propaga-
tion velocity is approximately 183ps/inch for internal
traces and 170ps/inch for surface traces. Thus, a driver
generating a control signal with a minimum transition
time of 1ns must be connected to the converter pin
through a trace shorter than 2.5 inches. This problem
becomes particularly difficult when shared control lines
are used and multiple reflections may occur. The solution
is to carefully terminate all transmission lines close to
their characteristic impedance.
Parallel termination near the LTC2439-1 pin will eliminate
this problem but will increase the driver power dissipation.
A series resistor between 27Ω and 56Ω placed near the
driver or near the LTC2439-1 pin will also eliminate this
20
OH
CC
> (V
– 0.5V), the CMOS input receiver draws additional
CC
– 0.4V)].
O
, CS and SCK in External SCK mode of
U
U
W
IL
< 0.4V and
U
O
, CS and
problem without additional power dissipation. The actual
resistor value depends upon the trace impedance and
connection topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The differential input and refer-
ence architecture reduce substantially the converter’s
sensitivity to ground currents.
Particular attention must be given to the connection of the
F
conversion clock. This clock is active during the conver-
sion time and the normal mode rejection provided by the
internal digital filter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals may result into DC gain and INL
errors. A normal mode signal of this frequency at the
converter input terminals may result into a DC offset error.
Such perturbations may occur due to asymmetric capaci-
tive coupling between the F
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the F
nals. When the F
converter, substantial AC current is flowing in the loop
formed by the F
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or refer-
ence. In this situation, the user must reduce to a minimum
the loop area for the F
the differential input and reference connections.
Driving the Input and Reference
The input and reference pins of the LTC2439-1 converter
are directly connected to a network of sampling capaci-
tors. Depending upon the relation between the differential
input voltage and the differential reference voltage, these
capacitors are switching between these four pins transfer-
ring small amounts of charge in the process. A simplified
equivalent circuit is shown in Figure 12.
For a simple approximation, the source impedance R
driving an analog input pin (IN
considered to form, together with R
O
signal when the LTC2439-1 is used with an external
O
O
signal trace and the input/reference sig-
connection trace, the termination and the
O
signal is parallel terminated near the
O
signal as well as the loop area for
O
signal trace and the converter
+
, IN
–
, REF
SW
+
or REF
and C
–
) can be
EQ
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(see
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