LTC2412IGN#PBF Linear Technology, LTC2412IGN#PBF Datasheet - Page 26

• Manufacturer Part Number: LTC2412IGN#PBF
• Description: IC ADC 2CH DIFF-IN 24BIT 16SSOP
• Manufacturer: Linear Technology

Specifications of LTC2412IGN#PBF

• Number Of Bits: 24
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
LTC2412
various values of source resistance imbalance between
the IN
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/ C) are
used for the external source impedance seen by IN
IN
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA ( 10nA max), results
26
–
, the expected drift of the dynamic current, offset and
+
Figure 17. Offset Error vs Common Mode Voltage
(V
Imbalance ( R
Large C
and IN
INCM
–100
–120
–20
–40
–60
–80
120
100
80
60
40
20
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
= IN
A: R
B: R
C: R
D: R
IN
–
Values (C
pins when large C
+
IN
IN
IN
IN
A
B
C
D
E
F
G
= IN
= +400
= +200
= +100
= 0
U
IN
–
= R
) and Input Source Resistance
V
REF
REF
IN
F
T
R
C
CC
O
+
A
IN
SOURCEIN
IN
SOURCEIN
+
= IN
V
–
= GND
= 25 C
= 5V
= 10 F
U
INCM
= 5V
= GND
–
1 F)
= V
(V)
– = 500
INCM
E: R
F: R
G: R
+ – R
IN
W
IN
IN
IN
values are used.
SOURCEIN
= –200
= –100
= –400
2412 F17
–) for
U
+
and
in a small offset shift. A 100 source resistance will create
a 0.1 V typical and 1 V maximum offset voltage.
Reference Current
In a similar fashion, the LTC2412 samples the differential
reference pins REF
charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can be
analyzed in the same two distinct situations.
For relatively small values of the external reference capaci-
tors (C
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for C
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (C
be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi con-
stant reference differential impedance. When F
(internal oscillator and 60Hz notch), the typical differential
reference resistance is 1.3M which will generate a gain
error of approximately 0.38ppm at full-scale for each ohm
of source resistance driving REF
HIGH (internal oscillator and 50Hz notch), the typical
differential reference resistance is 1.56M
generate a gain error of approximately 0.32ppm at full-
scale for each ohm of source resistance driving REF
REF
frequency f
typical differential reference resistance is 0.20 • 10
f
REF
scale. The effect of the source resistance on the two
reference pins is additive with respect to this gain error.
The typical +FS and –FS errors for various combinations
of source resistance seen by the REF
external capacitance C
shown in Figures 18, 19, 20 and 21.
EOSC
–
–
. When F
will result in 2.47 • 10
REF
and each ohm of source resistance drving REF
< 0.01 F), the voltage on the sampling capacitor
EOSC
REF
O
(external conversion clock operation), the
is driven by an external oscillator with a
will deteriorate the converter offset and
+
and REF
REF
–6
connected to these pins are
–
• f
transfering small amount of
EOSC
+
ppm gain error at full-
or REF
+
and REF
REF
> 0.01 F) may
–
. When F
which will
–
O
pins and
= LOW
+
O
+
2412f
12
or
or
=
/