LTC1864LIMS8#PBF Linear Technology, LTC1864LIMS8#PBF Datasheet
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LTC1864LIMS8#PBF
Specifications of LTC1864LIMS8#PBF
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LTC1864LIMS8#PBF Summary of contents
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... LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation. Supply Current vs Sampling Frequency 1000 ...
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LTC1864L/LTC1865L ABSOLUTE AXI U RATI GS Supply Voltage (V ) ................................................. 7V CC Ground Voltage Difference AGND, DGND LTC1865L MSOP Package ......... ±0.3V Analog Input ............... (GND – 0.3V Digital Input ................................ (GND – 0.3V) ...
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VERTER A D ULTIPLEXER CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are 2.7V 2.5V REF SCK SCK(MAX) PARAMETER CONDITIONS ...
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LTC1864L/LTC1865L RECO E DED OPERATI G CO DITIO S full operating temperature range, otherwise specifications are T SYMBOL PARAMETER V Supply Voltage CC f Clock Frequency SCK t Total Cycle Time CYC t Analog Input Sampling Time ...
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W U TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Sampling Frequency 1000 CONV LOW = 2µ 25° 2.7V CC 100 10 1 0.1 0.01 0 100 1000 SAMPLING FREQUENCY (kHz) 1864L/65L G01 ...
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LTC1864L/LTC1865L W U TYPICAL PERFOR A CE CHARACTERISTICS Change in Offset vs Reference Voltage 150kHz 25° 3. –5 –10 –15 – REFERENCE ...
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CTIO S LTC1864L V (Pin 1): Reference Input. The reference input defines REF the span of the A/D converter and must be kept free of noise with respect to GND. + – ...
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LTC1864L/LTC1865L U U FUNCTIONAL BLOCK DIAGRA PIN NAMES IN PARENTHESES REFER TO LTC1865L + IN (CH0) – IN (CH1) GND TEST CIRCUITS Load Circuit for dDO r f TEST POINT 3k SDO 20pF Voltage Waveforms ...
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U U APPLICATIO S I FOR ATIO LTC1864L OPERATION Operating Sequence The LTC1864L conversion cycle begins with the rising edge of CONV. After a period equal to t sion is finished. If CONV is left high after this time, the ...
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LTC1864L/LTC1865L U U APPLICATIO S I FOR ATIO LTC1865L OPERATION Operating Sequence The LTC1865L conversion cycle begins with the rising edge of CONV. After a period equal to t sion is finished. If CONV is left high after this time, ...
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U U APPLICATIO S I FOR ATIO GENERAL ANALOG CONSIDERATIONS Grounding The LTC1864L/LTC1865L should be used with an analog ground plane and single point grounding techniques. Do not use wire wrapping techniques to breadboard and evaluate the device. To achieve ...
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LTC1864L/LTC1865L U U APPLICATIO S I FOR ATIO sn18645L 18645Lfs ...
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U U APPLICATIO S I FOR ATIO Component Side Silk Screen for LTC1864L Evaluation Circuit Component Side Showing Traces (Note Wider Traces on Analog Side) Ground Layer with Separate Analog and Digital Grounds W U (Note Almost No Analog Traces ...
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LTC1864L/LTC1865L PACKAGE DESCRIPTIO 5.23 (.206) MIN 0.42 ± 0.04 (.0165 ± .0015) TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) GAUGE PLANE 0.18 (.077) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, ...
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... LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. ...
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... Slew Rate, 75µV/125µV Offset 140V/µs Slew Rate, 3.5nV/√Hz Noise, – 80dBc Distortion 350V/µs Slew Rate, – 90dBc Distortion at 5MHz www.linear.com ● 1µ SCK SDO ADC CONTROL 1864L/65L TA03 sn18645L 18645Lfs LT/TP 0403 2K • PRINTED IN USA © LINEAR TECHNOLOGY CORPORATION 2001 ...