LTC2415-1IGN#TRPBF Linear Technology, LTC2415-1IGN#TRPBF Datasheet - Page 31

• Manufacturer Part Number: LTC2415-1IGN#TRPBF
• Description: IC ADC 24BIT DIFFINPUT/REF16SSOP
• Manufacturer: Linear Technology

Specifications of LTC2415-1IGN#TRPBF

• Number Of Bits: 24
• Sampling Rate (per Second): 13.75
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
tance is 1.43M . When F
oscillator with a frequency f
clock operation), the typical differential reference resis-
tance is 0.20 • 10
resistance driving REF
2.47 • 10
resistance on the two reference pins is additive with
respect to this gain error. The typical +FS and –FS errors
for various combinations of source resistance seen by the
REF
connected to these pins are shown in Figures 25, 26, 27
and 28.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When F
100 of source resistance driving REF
into about 1.34ppm additional INL error. For the LTC2415,
when F
100 of source resistance driving REF
into about 1.1ppm additional INL error; and for the
LTC2415-1 operating with simultaneous 50Hz/60Hz re-
jection, every 100
additional 1.22ppm of additional INL error. When F
driven by an external oscillator with a frequency f
every 100
translates into about 8.73 • 10
error. Figure 26 shows the typical INL error due to the
source resistance driving the REF
+
and REF
O
O
= HIGH (internal oscillator and 50Hz notch), every
–6
= LOW (internal oscillator and 60Hz notch), every
• f
of source resistance driving REF
EOSC
–
ppm gain error. The effect of the source
pins and external capacitance C
U
12
/f
of source resistance leads to an
EOSC
Figure 29. INL vs Differential Input Voltage (V
Source Resistance (R
U
+
O
–6
EOSC
or REF
and each ohm of source
is driven by an external
• f
EOSC
+
W
(external conversion
or REF
+
+
ppm additional INL
–
or REF
or REF
–12
–15
will result in
15
12
–3
–6
–9
9
6
3
0
SOURCE
–0.5 –0.4–0.3–0.2–0.1 0 0.1 0.2 0.3 0.4 0.5
–
–
–
pins when
R
+
U
translates
translates
SOURCE
at REF
or REF
EOSC
= 100
O
REF
V
+
R
is
INDIF
SOURCE
and REF
–
,
/V
R
SOURCE
REFDIF
= 1000
large C
resistance on the two reference pins is additive with
respect to this INL error. In general, matching of source
impedance for the REF
gain or the INL error. The user is thus advised to minimize
the combined source impedance driving the REF
REF
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
0.5%. Such a specification can also be easily achieved by
an external clock. When relatively stable resistors
(50ppm/ C) are used for the external source impedance
seen by REF
current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
( 10nA max), results in a small gain error. A 100 source
resistance will create a 0.05 V typical and 0.5 V maxi-
mum full-scale error.
–
IN
for Large C
= 500
–
= IN
pins rather than to try to match it.
REF
+
2415 F29
– IN
values are used. The effect of the source
+
–
REF
and REF
) and Reference
V
REF+ = 5V
REF– = GND
V
F
C
T
O
CC
INCM
REF
A
Values (C
LTC2415/LTC2415-1
= GND
= 25 C
= 5V
= 10 F
= 0.5 • (IN
–
+
, the expected drift of the dynamic
and REF
REF
+
+ IN
–
1 F)
) = 2.5V
–
pins does not help the
sn2415 24151fs
31
+
and