LTC2418CGN Linear Technology, LTC2418CGN Datasheet - Page 22

• Manufacturer Part Number: LTC2418CGN
• Description: IC ADC 24BIT DIFF INPUT 28SSOP
• Manufacturer: Linear Technology

Specifications of LTC2418CGN

• Number Of Bits: 24
• Sampling Rate (per Second): 7.5
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 1mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP (0.150", 3.95mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

(INTERNAL)
APPLICATIO S I FOR ATIO
LTC2414/LTC2418
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the low power mode during the EOC
test. In order to allow the device to return to the low power
sleep state, CS must be pulled HIGH before the first rising
edge of SCK. In the internal SCK timing mode, SCK goes
HIGH and the device begins outputting data at time t
after the falling edge of CS (if EOC = 0) or t
goes LOW (if CS is LOW during the falling edge of EOC).
The value of t
oscillator (F
external oscillator of frequency f
3.6/f
device returns to the sleep state and the conversion result
is held in the internal static shift register.
If CS remains LOW longer than t
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data I/O cycle concludes
after the 32nd rising edge. The input data is then shifted in
via the SDI pin on the rising edge of SCK (including the first
rising edge) and the output data is shifted out of the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
22
SDO
SCK
SDI
CS
EOSC
CONVERSION
Hi-Z
DON’T CARE
. If CS is pulled HIGH before time t
O
EOCtest
= logic LOW or HIGH). If F
SLEEP
TEST EOC
is 23µs if the device is using its internal
U
SLEEP
Hi-Z
<t
EOCtest
U
(1)
BIT 31
EOC
BIT 30
EOCtest
(0)
EOSC
W
Figure 8. Internal Serial Clock, Single Cycle Operation
, then t
BIT 29
O
SIG
EOCtest
, the first rising
EN
is driven by an
EOCtest
0.1V TO V
REFERENCE
BIT 28
U
MSB
ANALOG
INPUTS
VOLTAGE
after EOC
EOCtest
SGL
1µF
2.7V TO 5.5V
EOCtest
CC
, the
BIT 27
•
•
•
•
•
•
11
12
21
28
10
ODD/
SIGN
9
1
8
is
DATA OUTPUT
V
REF
REF
CH0
CH7
CH8
CH15
COM
CC
•
•
•
•
•
•
LTC2414/
LTC2418
+
–
BIT 26
used to shift the conversion result into external circuitry.
EOC can be latched on the first rising edge of SCK and the
last bit of the conversion result on the 32nd rising edge of
SCK. After the 32nd rising edge, SDO goes HIGH (EOC =
1), SCK stays HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. If the device has not finished loading the
last input bit A0 of SDI by the time CS is pulled HIGH, the
address information is discarded and the previous ad-
dress is still kept. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.
A2
GND
SDO
SCK
SDI
CS
F
O
17
15
20
18
BIT 25
19
16
A1
4-WIRE
SPI INTERFACE
BIT 24
V
CC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
A0
DON’T CARE
BIT 6
LSB
V
CC
10k
PARITY
BIT 0
CONVERSION
Hi-Z
TEST EOC
241418fa
241418 F08
Hi-Z