LTC1410CSW Linear Technology, LTC1410CSW Datasheet - Page 7

• Manufacturer Part Number: LTC1410CSW
• Description: IC A/D CONV 12BIT SAMPLNG 28SOIC
• Manufacturer: Linear Technology

Specifications of LTC1410CSW

• Number Of Bits: 12
• Sampling Rate (per Second): 1.25M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 230mW
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LTC1410CS

APPLICATIONS
CONVERSION DETAILS
The LTC1410 uses a successive approximation algorithm
and an internal sample-and-hold circuit to convert an
analog signal to a 12-bit parallel output. The ADC is
complete with a precision reference and an internal clock.
The control logic provides easy interface to microproces-
sors and DSPs. (Please refer to the Digital Interface
section for the data format.)
Conversion start is controlled by the CS and CONVST
inputs. At the start of the conversion the successive
approximation register (SAR) is reset. Once a conversion
cycle has begun it cannot be restarted.
During the conversion, the internal differential 12-bit
capacitive DAC output is sequenced by the SAR from the
Most Significant Bit (MSB) to the Least Significant Bit
(LSB). Referring to Figure 1, the + A
connected to the sample-and-hold capacitors (C
during the acquire phase and the comparator offset is
nulled by the zeroing switches. In this acquire phase, a
minimum duration of 100ns will provide enough time for
the sample-and-hold capacitors to acquire the analog
signal. During the convert phase the comparator zeroing
switches open, putting the comparator into compare
mode. The input switches connect the C
to ground, transferring the differential analog input charge
TEST CIRCUITS
DBN
(A) Hi-Z TO V
1k
Load Circuits for Access Timing
OH
AND V
U
OL
TO V
C
L
INFORMATION
OH
U
DBN
(B) Hi-Z TO V
IN
W
and – A
SAMPLE
OL
5V
IN
AND V
1k
capacitors
inputs are
U
C
L
SAMPLE
OH
1410 TC01
TO V
OL
)
onto the summing junctions. This input charge is succes-
sively compared with the binarily-weighted charges sup-
plied by the differential capacitive DAC. Bit decisions are
made by the high speed comparator. At the end of a
conversion, the differential DAC output balances the + A
and – A
word) which represent the difference of + A
loaded into the 12-bit output latches.
– A
+A
DBN
IN
IN
IN
SAMPLE
SAMPLE
input charges. The SAR contents (a 12-bit data
+V
1k
(A) V
DAC
Figure 1. Simplified Block Diagram
Load Circuits for Output Float Delay
OH
–V
HOLD
HOLD
TO Hi-Z
DAC
+C
–C
–C
+C
SAMPLE
SAMPLE
DAC
100pF
DAC
SAR
DBN
ZEROING SWITCHES
+
–
HOLD
HOLD
12
COMP
(B) V
LATCHES
OUTPUT
LTC1410
IN
OL
5V
and – A
TO Hi-Z
1k
100pF
•
•
•
1410 TC02
IN
1410 F01
D11
D0
7
are
IN