LTC1279ISW Linear Technology, LTC1279ISW Datasheet - Page 14

• Manufacturer Part Number: LTC1279ISW
• Description: IC A/DCONV SAMPLNG W/SHTDN24SOIC
• Manufacturer: Linear Technology

Specifications of LTC1279ISW

• Number Of Bits: 12
• Sampling Rate (per Second): 600k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 120mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LTC1279IS

LTC1279
A
Timing and Control
Conversion start and data read operations are controlled
by three digital inputs: CS, CONVST and RD. Figure 11
shows the logic structure associated with these inputs. A
logic “0” for CONVST will start a conversion after the ADC
has been selected (i.e., CS is low). Once initiated, it cannot
be restarted until the conversion is complete. Converter
status is indicated by the BUSY output, and this is low
while conversion is in progress.
Figures 12 through 16 show several different modes of
operation. In modes 1a and 1b (Figures 12 and 13) CS and
RD are both tied low. The falling CONVST starts the
conversion. The data outputs are always enabled and data
can be latched with the BUSY rising edge. Mode 1a shows
operation with a narrow logic low CONVST pulse. Mode 1b
shows a narrow logic high CONVST pulse.
In mode 2 (Figure 14) CS is tied low. The falling CONVST
signal again starts the conversion. Data outputs are in
three-state until read by MPU with the RD signal. Mode 2
can be used for operation with a shared MPU databus.
14
PPLICATI
Figure 12. Mode 1a. CONVST Starts a Conversion. Data Ouputs Always Enabled. (CONVST =
O
U
CONVST
S
SHDN
CS = RD = 0
RD
CS
I FOR ATIO
CONVST
U
Figure 11. Internal Logic for Control Inputs CS, RD, CONVST and SHDN
BUSY
DATA
W
DB11 TO DB0
DATA (N – 1)
t
SAMPLE N
5
t
4
t
CONV
U
t
6
D
DB11 TO DB0
In Slow memory and ROM modes (Figures 15 and 16) CS
is tied low and CONVST and RD are tied together. The MPU
starts conversion and reads the output with the RD signal.
Conversions are started by the MPU or DSP (no external
sample clock).
In Slow memory mode the processor applies a logic low
to RD (= CONVST), starting the conversion. BUSY goes
low, forcing the processor into a WAIT state. The previous
conversion result appears on the data outputs. When the
conversion is complete, the new conversion results
appear on the data outputs; BUSY goes high, releasing the
processor; the processor applies a logic high to RD
(= CONVST) and reads the new conversion data.
In ROM mode, the processor applies a logic low to RD
(= CONVST), starting a conversion and reading the previ-
ous conversion result. After the conversion is complete,
the processor can read the new result (which will initiate
another conversion).
CLEAR
DATA N
FLOP
FLIP
SAMPLE N + 1
Q
BUSY
ACTIVE HIGH
ENABLE THREE-STATE OUTPUTS
DB11....DB0
CONVERSION
START (RISING
EDGE TRIGGER)
DB11 TO DB0
DATA (N + 1)
1279 F11
1279 F12
)