LTC1419AISW#TR Linear Technology, LTC1419AISW#TR Datasheet - Page 6

• Manufacturer Part Number: LTC1419AISW#TR
• Description: IC ADC 14BIT 800KSPS SHDN 28SOIC
• Manufacturer: Linear Technology

Specifications of LTC1419AISW#TR

• Number Of Bits: 14
• Sampling Rate (per Second): 800k
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 240mW
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

FU CTIO AL BLOCK DIAGRA
LTC1419
PI FU CTIO S
+ A
– A
V
with 1µF.
REFCOMP (Pin 4): 4.06V Reference Output. Bypass to
AGND with 10µF tantalum in parallel with 0.1µF or 10µF
ceramic.
AGND (Pin 5): Analog Ground.
D13 to D6 (Pins 6 to 13): Three-State Data Outputs. The
output format is 2’s complement.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
D5 to D0 (Pins 15 to 20): Three-State Data Outputs. The
output format is 2’s complement.
SHDN (Pin 21): Power Shutdown Input. Low selects
shutdown. Shutdown mode selected by CS. CS = 0 for
nap mode and CS = 1 for sleep mode.
RD (Pin 22): Read Input. This enables the output
drivers when CS is low.
6
REF
U
IN
IN
U
(Pin 3): 2.5V Reference Output. Bypass to AGND
(Pin 1): ±2.5V Positive Analog Input.
(Pin 2): ±2.5V Negative Analog Input.
U
REFCOMP
(4.096V)
DGND
AGND
– A
V
+A
U
REF
IN
IN
U
2k
REF AMP
2.5V REF
INTERNAL
CLOCK
W
SHDN
14-BIT CAPACITIVE DAC
SUCCESSIVE APPROXIMATION
C
C
CONVST
CONTROL LOGIC
SAMPLE
SAMPLE
REGISTER
CONVST (Pin 23): Conversion Start Signal. This active
low signal starts a conversion on its falling edge.
CS (Pin 24): Chip Select. The input must be low for the
ADC to recognize CONVST and RD inputs. CS also sets
the shutdown mode when SHDN goes low. CS and
SHDN low select the quick wake-up nap mode. CS high
and SHDN low select sleep mode.
BUSY (Pin 25): The BUSY output shows the converter
status. It is low when a conversion is in progress. Data
valid on the rising edge of BUSY.
V
with 10µF tantalum in parallel with 0.1µF or 10µF
ceramic.
DV
AV
with 10µF tantalum in parallel with 0.1µF or 10µF
ceramic.
SS
DD
DD
RD
(Pin 26): – 5V Negative Supply. Bypass to AGND
(Pin 27): 5V Positive Supply. Short to Pin 28.
(Pin 28): 5V Positive Supply. Bypass to AGND
CS
BUSY
14
ZEROING SWITCHES
+
–
COMP
OUTPUT LATCHES
1419 BD
•
•
•
AV
DV
V
D13
D0
SS
DD
DD
1419fb