LTC2242IUP-10#TRPBF Linear Technology, LTC2242IUP-10#TRPBF Datasheet - Page 20

• Manufacturer Part Number: LTC2242IUP-10#TRPBF
• Description: IC ADC 10BIT 250MSPS 64-QFN
• Manufacturer: Linear Technology

Specifications of LTC2242IUP-10#TRPBF

• Number Of Bits: 10
• Sampling Rate (per Second): 250M
• Data Interface: Parallel
• Number Of Converters: 1
• Power Dissipation (max): 975mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-WFQFN, Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIONS INFORMATION
LTC2242-10
Table 1. Output Codes vs Input Voltage
Digital Output Modes
The LTC2242-10 can operate in several digital output
modes: LVDS, CMOS running at full speed, and CMOS
demultiplexed onto two buses, each of which runs at half
speed. In the demultiplexed CMOS modes the two buses
(referred to as bus A and bus B) can either be updated on
alternate clock cycles (interleaved mode) or simultaneously
(simultaneous mode). For details on the clock timing, refer
to the timing diagrams.
The LVDS pin selects which digital output mode the part
uses. This pin has a four-level logic input which should
be connected to GND, 1/3V
resistor divider can be used to set the 1/3V
logic values. Table 2 shows the logic states for the LVDS
pin.
Table 2. LVDS Pin Function
LVDS
GND
1/3V
2/3V
V
20
DD
>+1.000000V
<–1.000000V
+0.998047V
+0.996094V
+0.001953V
–0.001953V
–0.003906V
–0.998047V
–1.000000V
(2V Range)
A
DD
DD
0.000000V
IN
+
– A
IN
–
DIGITAL OUTPUT MODE
Full-Rate CMOS
Demultiplexed CMOS, Simultaneous Update
Demultiplexed CMOS, Interleaved Update
LVDS
OF
1
0
0
0
0
0
0
0
0
1
(Offset Binary)
11 1111 1111
11 1111 1111
11 1111 1110
10 0000 0001
10 0000 0000
01 1111 1111
01 1111 1110
00 0000 0001
00 0000 0000
00 0000 0000
DD
D9 – D0
, 2/3V
DD
or V
(2’s Complement)
DD
01 1111 1111
01 1111 1111
01 1111 1110
00 0000 0001
00 0000 0000
11 1111 1111
11 1111 1110
10 0000 0001
10 0000 0000
10 0000 0000
DD
. An external
D9 – D0
or 2/3V
DD
Digital Output Buffers (CMOS Modes)
Figure 13a shows an equivalent circuit for a single
output buffer in the CMOS output mode. Each buffer is
powered by OV
ADC power and ground. The additional N-channel transistor
in the output driver allows operation down to voltages as
low as 0.5V. The internal resistor in series with the output
makes the output appear as 50Ω to external circuitry and
may eliminate the need for external damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2242-10 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an 74VCX245
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF .
Lower OV
from the digital outputs.
Digital Output Buffers (LVDS Mode)
Figure 13b shows an equivalent circuit for a differential
output pair in the LVDS output mode. A 3.5mA current is
steered from OUT
±350mV differential voltage across the 100Ω termination
resistor at the LVDS receiver. A feedback loop regulates
the common mode output voltage to 1.25V. For proper
operation each LVDS output pair needs an external 100Ω
termination resistor, even if the signal is not used (such as
OF
board traces for each LVDS output pair should be routed
close together. To minimize clock skew all LVDS PC board
traces should have about the same length.
+
/OF
–
or CLKOUT
DD
voltages will also help reduce interference
DD
+
and OGND, which are isolated from the
to OUT
+
/CLKOUT
–
or vice versa which creates a
–
). To minimize noise the PC
224210fc