LTC2241IUP-12#TRPBF Linear Technology, LTC2241IUP-12#TRPBF Datasheet - Page 6

IC ADC 12BIT 210MSPS 64-QFN

LTC2241IUP-12#TRPBF

Manufacturer Part Number
LTC2241IUP-12#TRPBF
Description
IC ADC 12BIT 210MSPS 64-QFN
Manufacturer
Linear Technology
Datasheet

Specifications of LTC2241IUP-12#TRPBF

Number Of Bits
12
Sampling Rate (per Second)
210M
Data Interface
Parallel
Number Of Converters
1
Power Dissipation (max)
805mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-WFQFN, Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTC2241IUP-12#TRPBFLTC2241IUP-12
Manufacturer:
LT/凌特
Quantity:
20 000
Company:
Part Number:
LTC2241IUP-12#TRPBFLTC2241IUP-12#PBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
ELECTRICAL CHARACTERISTICS
LTC2241-12
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above V
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V
Note 4: V
ENC
drive, unless otherwise noted.
Note 5: Integral nonlinearity is defi ned as the deviation of a code from
a “best straight line” fi t to the transfer curve. The deviation is measured
from the center of the quantization band.
TYPICAL PERFORMANCE CHARACTERISTICS
6
–1.0
–0.2
–0.4
–0.6
–0.8
+
1.0
0.8
0.6
0.4
0.2
/ENC
0
0
Integral Nonlinearity
DD
= 2V
= 2.5V, f
1024
P-P
sine wave, input range = 2V
SAMPLE
OUTPUT CODE
2048
= 210MHz, LVDS outputs, differential
3072
224112 G01
4096
DD
P-P
without latchup.
with differential
–0.2
–0.4
–0.6
–1.0
–0.8
1.0
0.8
0.6
0.4
0.2
0
Differential Nonlinearity
0
DD
, they
1024
OUTPUT CODE
2048
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code fl ickers between 0000 0000 0000 and 1111 1111 1111 in
2’s complement output mode.
Note 7: Guaranteed by design, not subject to test.
Note 8: Recommended operating conditions.
Note 9: V
sine wave, input range = 1V
Note 10: SNR minimum and typical values are for LVDS mode. Typical
values for CMOS mode are typically 0.3dB lower.
Note 11: SFDR minimum values are for LVDS mode. Typical values are for
both LVDS and CMOS modes.
Note 12: SINAD minimum and typical values are for LVDS mode. Typical
values for CMOS mode are typically 0.3dB lower.
3072
DD
= 2.5V, f
224112 G02
(T
4096
A
SAMPLE
= 25°C unless otherwise noted, Note 4)
P-P
–100
–110
= 210MHz, differential ENC
–60
–70
–10
–20
–30
–40
–50
–80
–90
0
with differential drive, output C
0
8192 Point FFT, f
–1dB, 2V Range, LVDS Mode
20
FREQUENCY (MHz)
40
IN
60
+
= 5MHz,
/ENC
LOAD
80
= 2V
224112 G03
P-P
= 5pF .
224112fb
100

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