CS5522-ASZR Cirrus Logic Inc, CS5522-ASZR Datasheet - Page 46

• Manufacturer Part Number: CS5522-ASZR
• Description: IC ADC 24BIT 2CH 20-SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5522-ASZR

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 14.8mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

verter stays constant but the number of codes af-
fected is doubled because the code size has been
reduced by half.
The converter input ranges are specified with a
voltage reference of 2.5 V. The device can be op-
erated with the reference tied directly to the +5 V
supply. When this is done, the input span of the in-
put ranges is doubled; the 25 mV range actually be-
comes a 50 mV range. The gain register can be set
to 2.0 (shift contents left one bit) and the input
range will be scaled back to 25 mV. Since the gain
register can actually be as great as 4-2
one could scale the input span on the 25 mV range
to accept an analog full-scale span of about
6.25 mV. This is useful for ratiometric bridge mea-
surement of low-level differential outputs.
The gain register can also be scaled manually to a
value lower than 1.0. It is not recommended to use
the devices with the gain register scaled lower than
0.6. This can enable the converter to accept a
40 mV input signal on the 25 mV range when using
a voltage reference of 2.5 V. Caution though in
scaling the gain register below 1.0 on the 100 mV,
2.5 and 5 volt ranges as the analog signal path into
the converter may saturate before the expected
full-scale code output is produced by the converter.
Note that digital gain scaling will directly influence
the number of digital output codes affected by
noise. The effects can be analytically determined
by calculating the size of the codes (V/Count)
which result from a given gain scaling condition
and relating the amount of noise in the converter
relative to the determined code size. The evalua-
tion board for the converter is a useful tool to aid
the assessment of noise performance with various
voltage reference values, input range settings, and
gain register settings. The evaluation board sup-
ports noise analysis through data capture and noise
histogram analysis.
46
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decimal,
1.10 Getting Started
The CS5521/22/23/24/28 have many features.
From a software programmer’s perspective, what
should be done first? To begin, a 32.768 kHz crys-
tal takes approximately 500 ms to start-up. To ac-
commodate for this, it is recommended that a
software delay greater than 500 ms precede the
processor’s ADC initialization code before any
registers are accessed in the ADC. This delay time
is dependent on the start-up delay of the clock
source. If a CMOS clock source with no start-up
delay is being used to drive the ADC, then this de-
lay is not necessary.
Once the oscillator is started, the following se-
quence of instructions should be performed to
guarantee the converter begins proper operation:
1) After power is applied, initialize the serial port
2) Write a ‘1’ to the reset bit (RS) of the configu-
3) Read the configuration register to determine if
4) When the RV bit has been set to ‘1’, reset the
Once the RS bit has been set to ‘0’, the ADC is
placed in the command state were it waits for a val-
id command to execute. The next step is to load the
configuration register and then the channel setup
registers with conditions that you have decided. If
you need to do a factory calibration, perform offset
and gain calibrations for each channel that is to be
used. Then off-load the offset and gain register
contents into EEPROM. These registers can then
using the serial port synchronization sequence.
ration register to reset the converter.
the reset valid bit (RV) is set to ‘1’. If the RV
bit is not set, the configuration register should
be read again.
RS bit back to ‘0’ by writing 0x000000 to the
configuration register. Note that while the RS
bit is set to ‘1’ all other register bits in the ADC
will be reset to their default state, and the RS bit
must be set to ‘0’ for normal operation of the
converters.
CS5521/22/23/24/28
DS317F8