AD7495AR-REEL7 Analog Devices Inc, AD7495AR-REEL7 Datasheet - Page 17
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AD7495AR-REEL7
Manufacturer Part Number
AD7495AR-REEL7
Description
IC ADC 12BIT SRL LP W/REF 8-SOIC
Manufacturer
Analog Devices Inc
Datasheet
1.AD7475ARMZ-REEL7.pdf
(24 pages)
Specifications of AD7495AR-REEL7
Rohs Status
RoHS non-compliant
Number Of Bits
12
Sampling Rate (per Second)
1M
Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
10.5mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
To exit this operating mode and power up the AD7475/AD7495
again, a dummy conversion is performed. On the falling edge of
CS , the device begins to power up and continues to power up as
long as CS is held low until after the falling edge of the tenth
SCLK. The device is fully powered up once 16 SCLKs have
elapsed, and valid data results from the next conversion, as
shown in Figure 21. If CS is brought high before the second
falling edge of SCLK, the AD7475/AD7495 go back into partial
power-down again. This avoids accidental power-up due to
glitches on the CS line; although the device may begin to power
up on the falling edge of CS , it powers down again on the rising
edge of CS . If in partial power-down and CS is brought high
between the second and tenth falling edges of SCLK, the device
enters full power-down mode.
Power-Up Time
The power-up time of the AD7475/AD7495 from partial
power-down is typically 1 μs, which means that with any
frequency of SCLK up to 20 MHz, one dummy cycle is
sufficient to allow the device to power up from partial power-
down. Once the dummy cycle is complete, the ADC is fully
powered up and the input signal is acquired properly. The quiet
time, t
goes back into three-state after the dummy conversion to the
next falling edge of CS . When running at a 1 MSPS throughput
rate, the AD7475/AD7495 power up and acquire a signal within
±0.5 LSB in one dummy cycle, 1 μs.
QUIET,
SDATA
SDATA
SCLK
SCLK
CS
CS
must still be allowed from the point where the bus
A
1
1
2
PARTIAL POWER-DOWN
THE PART BEGINS
INVALID DATA
THE PART ENTERS
TO POWER UP
INVALID DATA
10
10
THREE-STATE
Figure 21. Exiting Partial Power-Down Mode
Figure 22. Entering Full Power-Down Mode
16
16
Rev. B | Page 17 of 24
THE PART IS FULLY
THE PART BEGINS
When powering up from the power-down mode with a dummy
cycle, as in Figure 21, the track-and-hold that was in hold mode
while the part was powered down returns to track mode after
the first SCLK edge the part receives after the falling edge of CS .
This is shown as Point A in Figure 21. Although at any SCLK
frequency one dummy cycle is sufficient to power up the device
and acquire V
cycle of 16 SCLKs must always elapse to power up the device
and fully acquire V
and acquire the input signal. If, for example, a 5 MHz SCLK
frequency were applied to the ADC, the cycle time would be
3.2 μs. In one dummy cycle, 3.2 μs, the part would be powered
up and V
SCLK, only 5 SCLK cycles would have elapsed. At this stage,
the ADC would be fully powered up and the signal acquired.
In this case, the CS can be brought high after the tenth SCLK
falling edge and brought low again after a time, t
the conversion.
FULL POWER-DOWN MODE
Full power-down mode is intended for use in applications
where slower throughput rates are required than that in the
partial power-down mode, because power up from a full power-
down would not be complete in just one dummy conversion.
This mode is more suited to applications where a series of
conversions performed at a relatively high throughput rate are
followed by a long period of inactivity and therefore power
down. When the AD7475/AD7495 are in full power-down, all
analog circuitry is powered down.
TO POWER UP
POWERED UP
1
1
2
IN
INVALID DATA
fully acquired. However, after 1 μs with a 5 MHz
IN
, it does not necessarily mean that a full dummy
IN
; 1 μs is sufficient to power up the device
VALID DATA
FULL POWER-DOWN
10
THE PART ENTERS
THREE-STATE
AD7475/AD7495
16
16
QUIET,
to initiate