CS5506-BSZ Cirrus Logic Inc, CS5506-BSZ Datasheet - Page 9

• Manufacturer Part Number: CS5506-BSZ
• Description: IC ADC 20BIT 4CH 24-SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5506-BSZ

• Number Of Converters: 1
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Number Of Bits: 20
• Sampling Rate (per Second): 100
• Data Interface: Serial
• Power Dissipation (max): 4.5mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 4
• Architecture: Delta-Sigma
• Conversion Rate: 100 SPs
• Resolution: 20 bit
• Input Type: Differential
• Interface Type: Dual Serial
• Voltage Reference: 2.5 V
• Maximum Power Dissipation: 4.5 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 3.3 V, 5 V
• Minimum Operating Temperature: - 40 C
• Package: 24SOIC
• Sampling Rate: 0.1 KSPS
• Number Of Adcs: 1
• Number Of Analog Inputs: 4
• Digital Interface Type: Serial
• Polarity Of Input Voltage: Unipolar|Bipolar
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

5V SWITCHING CHARACTERISTICS
VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; C
Notes: 16. If CS is returned high before all data bits are output, the SDATA and SCLK outputs will complete the
DS59F7
DS59F7
SSC Mode (M/SLP = VD+)
Access Time:
SDATA Delay Time:
SCLK Delay Time
Serial Clock (Out)
Output Float Delay:
SEC Mode (M/SLP = DGND)
Serial Clock (In)
Serial Clock (In)
Access Time:
Maximum Delay time:
Output Float Delay:
17. If CS is activated asynchronously to DRDY, CS will not be recognized if it occ urs when DRDY is high
18. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the
current data bit and then go to high impedance.
for 2 clock cycles. The propagation delay time may be as great as 2 f clk cycles plus 200 ns. T o
guarantee proper clocking of SDATA when using asynchronous CS, SCLK(i) should not be taken high
sooner than 2 f clk + 200 ns after CS goes low.
serial port shifting mechanism before falling edges can be recognized.
CS Low to SDATA out (DRDY = low)
Parameter
CS high to output Hi-Z (Note 16)
CS high to output Hi-Z (Note 16)
DRDY falling to MSB (CS = low)
CS Low to data valid (Note 17)
SDATA MSB bit to SCLK rising
SCLK falling to next SDATA bit
SCLK falling to new SDATA bit
SCLK falling to SDATA Hi-Z
SCLK rising to SDATA Hi-Z
Pulse Width High
Pulse Width High
Pulse Width Low
Pulse Width Low
(Note 18)
(T
A
= T
MIN
Symbol
t
t
f
t
L
t
t
t
t
csd1
csd2
t
t
t
t
t
t
t
dd1
ph1
sclk
ph2
dd2
cd1
dfd
fd1
fd2
fd3
fd4
pl1
pl2
to T
= 50 pF.) (Note 2)
MAX;
Min
200
200
VA+, VD+ = 5V ± 10%;
0
-
-
-
-
-
-
-
-
-
-
-
-
2/f
1/f
1/f
1/f
1/f
Typ
150
160
80
60
60
-
-
-
-
-
clk
clk
clk
clk
clk
CS5505/6/7/8
CS5505/6/7/8
2/fclk
3/f
2/f
Max
250
200
310
150
300
2.5
-
-
-
-
-
-
clk
clk
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
9
9