MAX195BEWE+T Maxim Integrated Products, MAX195BEWE+T Datasheet - Page 16

• Manufacturer Part Number: MAX195BEWE+T
• Description: IC ADC 16BIT 85KSPS 16-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX195BEWE+T

• Number Of Bits: 16
• Sampling Rate (per Second): 85k
• Data Interface: QSPI™, Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 80mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

If ±15V supplies are unavailable, Figure 16’s circuit
works very well with the ±5V analog supplies used by
the MAX195. The MAX410 has a minimum ±3.5V com-
mon-mode input range, with a similar output voltage
swing, which allows use of a reference voltage up to
3.5V. The offset voltage (250µV) is about 2LSB. The
drift (1µV/°C), unity-gain bandwidth (28MHz), and low
voltage noise (2.4nV/ Hz) are appropriate for 16-bit
performance.
Figure 17. MAX195 Connection to QSPI Processor Clocking
Data Out During Conversions
16-Bit, 85ksps ADC with 10µA Shutdown
Figure 16. ±5V Buffer for AC/DC Use Has ±3.5V Swing
16
IN
______________________________________________________________________________________
* THE USE OF THESE SIGNALS ADDS FLEXIBILITY AND FUNCTIONALITY
BUT IS NOT REQUIRED TO IMPLEMENT THE INTERFACE.
2
3
QSPI
GPT
MAX410
+5V
-5V
PCS0
MISO
*OC3
*OC2
SCK
*IC1
7
4
510
6
0.1 F
0.1 F
22
CS
CONV
CLK
DOUT
SCLK
BP/UP/SHDN
EOC
RESET
MAX195
0.01 F
AIN
The two basic interface modes are defined according
to whether serial data is received during the conversion
(clocked with CLK, SCLK unused) or in bursts between
conversions (clocked with SCLK). Each mode is pre-
sented interfaced to a QSPI processor, but is also com-
patible with SPI.
In this mode, each data bit is read from the MAX195
during the conversion as it is determined. SCLK is
grounded and CLK is used as both the conversion
clock and the serial data clock. Figure 17 shows a
QSPI processor connected to the MAX195 for use in
this mode and Figure 18 is the associated timing dia-
gram.
In addition to the standard QSPI interface signals, gen-
eral I/O lines are used to monitor EOC and to drive
BP/UP/SHDN and RESET. The two general output pins
may not be necessary for a given application and, if I/O
lines are unavailable, the EOC connection can be omit-
ted as well.
The EOC signal is monitored during calibration to
determine when calibration is finished and before
beginning a conversion to ensure the MAX195 is not in
mid-conversion, but it is possible for a system to ignore
EOC completely. On power-up or after pulsing RESET
low, the µP must provide 14,000 CLK cycles to com-
plete the calibration sequence (Figure 2). One way to
do this is to toggle CLK and monitor EOC until it goes
low, but it is possible to simply count 14,000 CLK
cycles to complete the calibration. Similarly, it is
unnecessary to check the status of EOC before begin-
ning a conversion if you are sure the last conversion is
complete. This can be done by ensuring that every
conversion consists of at least 20 CLK cycles.
Data is clocked out of the MAX195 on CLK’s falling
edge and can be clocked into the µP on the rising
edge or the following falling edge. If you clock data in
on the rising edge (SPI/QSPI with CPOL = 0 and CPHA
= 0; standard MicroWire™: Hitachi H8), the maximum
CLK rate is given by:
where t
and t
MicroWire is a trademark of National Semiconductor Corp.
Operating Modes and SPI/QSPI Interfaces
SD
CD
is the data setup time for your µP.
is the MAX195’s CLK-to-DOUT valid delay
f
CLK(max)
Conversion and Data Transfer)
= /
1
2
t
Mode 1 (Simultaneous
CD
1
+ t
SD