CS5102A-BLZ Cirrus Logic Inc, CS5102A-BLZ Datasheet - Page 35

• Manufacturer Part Number: CS5102A-BLZ
• Description: IC ADC 16BIT 100/20KHZ 28-PLCC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5102A-BLZ

• Number Of Bits: 16
• Sampling Rate (per Second): 20k
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 65mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 598-1079-5

8.4
8.5
8.6
8.7
DS45F6
SCLK - Serial Clock, PIN 14.
RST - Reset, PIN 2.
AIN1, AIN2 - Channel 1 and 2 Analog Inputs, PINS 19 and 24.
VREF - Voltage Reference, PIN 20.
STBY - Standby (Calibrating), PIN 5.
SDATA - Serial Output, PIN 15.
SSH/SDL - Simultaneous Sample/Hold / Serial Data Latch, PIN 11.
TRK1, TRK2 - Tracking Channel 1, Tracking Channel 2, PINS 8 and 9.
REFBUF - Reference Buffer Output, PIN 21.
TEST - Test, PIN 26.
Serial data changes status on a falling edge of this input, and is valid on a rising edge. When SCKMOD
is high SCLK acts as an input. When SCKMOD is low the CS5101A or CS5102A generates its own
serial clock at ¼ the master clock frequency and SCLK is an output.
When taken low, all internal digital logic is reset. Upon returning high, a full calibration sequence is
initiated which takes 11,528,160 CLKIN cycles (CS5101A) or 2,882,040 CLKIN cycles (CS5102A) to
complete. During calibration, the HOLD input will be ignored. The CS5101A or CS5102A must be reset
at power-up for calibration, however; calibration is maintained during SLEEP mode, and need not be
repeated when resuming normal operation.
Analog Inputs
Analog input connections for the left and right input channels.
The analog reference voltage which sets the analog input range. In unipolar mode VREF sets full-scale;
in bipolar mode its magnitude sets both positive and negative full-scale.
Digital Outputs
Indicates calibration status after reset. Remains low throughout the calibration sequence and returns
high upon completion.
Presents each output data bit on a falling edge of SCLK. Data is valid to be latched on the rising edge
of SCLK.
Used to control an external sample/hold amplifier to achieve simultaneous sampling between channels.
In FRN and SSC modes (SCLK is an output), this signal provides a convenient latch signal which forms
the 16 data bits. This can be used to control external serial to parallel latches, or to control the serial
port in a DSP.
Falls low at the end of a conversion cycle, indicating the acquisition phase for the corresponding
channel. The TRK1 or TRK2 pin will return high at the beginning of conversion for that channel.
Analog Outputs
Reference buffer output.
Miscellaneous
Allows access to the CS5101A's and the CS5102A's test functions which are reserved for factory use.
Must be tied to VD+.
CS5101A CS5102A
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