AD9640BCPZ-125 Analog Devices Inc, AD9640BCPZ-125 Datasheet - Page 6

• Manufacturer Part Number: AD9640BCPZ-125
• Description: IC ADC 14BIT 125MSP 1.8V 64LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD9640BCPZ-125

• Design Resources: Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 846mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• For Use With: AD9640-150EBZ - BOARD EVALUATION AD9640 150MSPS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9640
ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ-150
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ACCURACY
MATCHING CHARACTERISTIC
TEMPERATURE DRIFT
INTERNAL VOLTAGE REFERENCE
INPUT REFERRED NOISE
ANALOG INPUT
VREF INPUT RESISTANCE
POWER SUPPLIES
POWER CONSUMPTION
1
2
3
4
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure.
The maximum limit applies to the combination of I
Standby power is measured with a dc input and with the CLK pins (CLK+, CLK
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Offset Error
Gain Error
Offset Error
Gain Error
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
VREF = 1.0 V
Input Span, VREF = 1.0 V
Input Capacitance
Supply Voltage
Supply Current
DC Input
Sine Wave Input
Sine Wave Input
Standby Power
Power-Down Power
AVDD, DVDD
DRVDD (CMOS Mode)
DRVDD (LVDS Mode)
I
I
I
I
I
AVDD
DVDD
DRVDD
DRVDD
DRVDD
1
1
, 3
,
1
1
1
3
(3.3 V CMOS)
(1.8 V CMOS)
(1.8 V LVDS)
4
1
1
(DRVDD = 1.8 V)
(DRVDD = 3.3 V)
2
1
1
Temperature
Full
Full
Full
Full
Full
25°C
Full
25°C
25°C
25°C
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AVDD
and
IDVDD
currents.
Rev. B | Page 6 of 52
Min
14
1.7
1.7
1.7
AD9640ABCPZ-125/
−
AD9640BCPZ-125
) inactive (set to AVDD or AGND).
Guaranteed
Typ
±0.3
±0.2
±0.4
±0.1
±95
±0.4
±2
±15
±2
7
1.3
2
8
6
1.8
3.3
1.8
385
42
44
22
56
750
810
910
77
2.5
Max
±0.6
±3.0
±0.9
±5.0
±0.7
±0.6
±15
1.9
3.6
1.9
470
846
6
Min
14
1.7
1.7
1.7
AD9640ABCPZ-150
±0.4
±0.2
Typ
±0.3
±0.2
−0.4/+0.6
±2
±15
±95
±3
7
1.3
2
8
6
1.8
3.3
1.8
419
50
53
27
57
820
895
1000
77
2.5
AD9640BCPZ-150
Guaranteed
Max
±0.6
±3.0
−0.95/+1.5
±5.0
±0.7
±0.6
1.9
3.6
1.9
517
938
6
±15
/
Unit
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
% FSR
% FSR
ppm/°C
ppm/°C
mV
mV
LSB rms
V p-p
pF
kΩ
V
V
V
mA
mA
mA
mA
mW
mW
mW
mW
mW