ADC12132CIMSA National Semiconductor, ADC12132CIMSA Datasheet - Page 34

• Manufacturer Part Number: ADC12132CIMSA
• Description: IC ADC 12BIT 20-SSOP
• Manufacturer: National Semiconductor

Specifications of ADC12132CIMSA

• Number Of Bits: 12
• Sampling Rate (per Second): 114k
• Data Interface: NSC MICROWIRE™, Serial
• Number Of Converters: 4
• Power Dissipation (max): 33mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SSOP (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC12132CIMSA

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4.0 ANALOG INPUT VOLTAGE RANGE
The ADC12130/2/8's fully differential ADC generate a two's
complement output that is found by using the equation shown
below:
Round off to the nearest integer value between −4096 to 4095
if the result of the above equation is not a whole number.
Examples are shown in the table below:
5.0 INPUT CURRENT
At the start of the acquisition window (t
flows into or out of the analog input pins (A/DIN1 and A/DIN2)
depending upon the input voltage polarity. The analog input
pins are CH0–CH7 and COM when A/DIN1 is tied to
MUXOUT1 and A/DIN2 is tied to MUXOUT2. The peak value
of this input current will depend upon the actual input voltage
applied, the source impedance and the internal multiplexer
switch on resistance. With MUXOUT1 tied to A/DIN1 and
MUXOUT2 tied to A/DIN2 the internal multiplexer switch on
resistance is typically 1.6 kΩ. The A/DIN1 and A/DIN2 mux
on resistance is typically 750Ω.
6.0 INPUT SOURCE RESISTANCE
For low impedance voltage sources (<600Ω), the input charg-
ing current will decay, before the end of the S/H's acquisition
time of 2 μs (10 CCLK periods with f
that will not introduce any conversion errors. For high source
impedances, the S/H's acquisition time can be increased to
18 or 34 CCLK periods. For less ADC accuracy and/or slower
CCLK frequencies the S/H's acquisition time may be de-
+4.096V
+4.096V
+4.096V
for (12-bit) resolution the Output Code =
+2.5V
V
REF
+
FIGURE 17. V
V
+1V
REF
0V
0V
0V
−
+2.499V +2.500V 1,1111,1111,1111
+1.5V
V
+3V
0V
IN
+
REF
Operating Range
+4.096V 1,0000,0000,0000
V
0V
0V
IN
−
CK
A
= 5 MHz), to a value
) a charging current
0,1111,1111,1111
0,1011,1011,1000
Code Output
Digital
1207944
34
creased to 6 CCLK periods. To determine the number of clock
periods (N
source impedance for the various resolutions the following
equations can be used:
Where f
and R
ple, operating with a resolution of 12 Bits + sign, a 5 MHz clock
frequency and maximum acquisition time of 34 conversion
clock periods the ADC's analog inputs can handle a source
impedance as high as 6 kΩ. The acquisition time may also be
extended to compensate for the settling or response time of
external circuitry connected between the MUXOUT and
A/DIN pins.
An acquisition starts at a falling edge of SCLK and ends at a
rising edge of CCLK (see timing diagrams). If SCLK and
CCLK are asynchronous, one extra CCLK clock period may
be inserted into the programmed acquisition time for synchro-
nization. Therefore, with asynchronous SCLK and CCLK, the
acquisition time will change from conversion to conversion.
7.0 INPUT BYPASS CAPACITANCE
External capacitors (0.01 μF–0.1 μF) can be connected be-
tween the analog input pins, CH0–CH7, and analog ground
to filter any noise caused by inductive pickup associated with
long input leads. These capacitors will not degrade the con-
version accuracy.
8.0 NOISE
The leads to each of the analog multiplexer input pins should
be kept as short as possible. This will minimize input noise
and clock frequency coupling that can cause conversion er-
rors. Input filtering can be used to reduce the effects of the
noise sources.
9.0 POWER SUPPLIES
Noise spikes on the V
version errors; the comparator will respond to the noise. The
ADC is especially sensitive to any power supply spikes that
occur during the Auto Zero or linearity correction. The mini-
mum power supply bypassing capacitors recommended are
low inductance tantalum capacitors of 10 μF or greater par-
alleled with 0.1 μF monolithic ceramic capacitors. More or
different bypassing may be necessary depending upon the
overall system requirements. Separate bypass capacitors
should be used for the V
close as possible to these pins.
10.0 GROUNDING
The ADC12130/2/8's performance can be maximized through
proper grounding techniques. These include the use of sep-
arate analog and digital areas of the board with analog and
digital components and traces located only in their respective
areas. Bypass capacitors of 0.01 µF and 0.1 µF surface mount
capacitors and a 10 µF are recommended at each of the pow-
er supply pins for best performance. These capacitors should
be located as close to the bypassed pin as practical, espe-
cially the smaller value capacitors.
11.0 CLOCK SIGNAL LINE ISOLATION
The ADC12130/2/8's performance is optimized by routing the
analog input/output and reference signal conductors as far as
possible from the conductors that carry the clock signals to
the CCLK and SCLK pins. Maintaining a separation of at least
7 to 10 times the height of the clock trace above its reference
plane is recommended.
12 Bit + Sign N
S
is the external source resistance in kΩ. As an exam-
CK
c
is the conversion clock (CCLK) frequency in MHz
) required for the acquisition time with a specific
C
= [R
A
+
and V
S
A
+
+ 2.3] × f
and V
D
+
supply lines can cause con-
D
+
CK
supplies and placed as
× 0.824