LTC1091CN8#PBF Linear Technology, LTC1091CN8#PBF Datasheet - Page 22

IC DATA ACQ SYS 10BIT 2CH 8-DIP

LTC1091CN8#PBF

Manufacturer Part Number
LTC1091CN8#PBF
Description
IC DATA ACQ SYS 10BIT 2CH 8-DIP
Manufacturer
Linear Technology
Type
Data Acquisition System (DAS), ADCr
Datasheet

Specifications of LTC1091CN8#PBF

Resolution (bits)
10 b
Data Interface
Serial
Voltage Supply Source
Single Supply
Voltage - Supply
4.5 V ~ 10 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
8-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Sampling Rate (per Second)
-

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“–” Input Settling
At the end of the sample phase the input capacitor switches
to the “–” input and the conversion starts (see Figure 8).
During the conversion, the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
conversion result. However, it is critical that the “–” input
voltage settle completely during the first CLK cycle of the
conversion time and be free of noise. Minimizing R
and C2 will improve settling time. If large “–” input source
resistance must be used, the time allowed for settling can
be extended by using a slower CLK frequency. At the
maximum CLK rate of 500kHz, R
C2 < 20pF will provide adequate settling.
A
22
LTC1091/LTC1092
LTC1093/LTC1094
“+” INPUT
“–” INPUT
PPLICATI
D
CLK
OUT
D
CS
IN
O
U
S
I FOR ATIO
U
START
SOURCE
W
Figure 8. “+” and “–” Input Settling Windows
SGL/DIFF
< 1k
U
SOURCE
and
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 8). Again, the “+” and “–” input sampling times
can be extended as previously described to accommodate
slower op amps. Most op amps, including the LT1006 and
LT1013 single supply op amps, can be made to settle well
even with the minimum settling windows of 3 s (“+”
input) and 2 s (“–” input) which occur at the maximum
clock rate of 500kHz. Figures 9 and 10 show examples of
adequate and poor op amp settling.
1ST BIT TEST “–” INPUT MUST
SAMPLE
SETTLE DURING THIS TIME
“+” INPUT MUST
SETTLE DURING
THIS TIME
MSBF
t
SMPL
HOLD
DON‘T CARE
t
CONV
1091-4 F08
B9

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