MAX1358BETL+ Maxim Integrated Products, MAX1358BETL+ Datasheet - Page 39

• Manufacturer Part Number: MAX1358BETL+
• Description: IC DAS 16BIT 40-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Data Acquisition System (DAS)r

Specifications of MAX1358BETL+

• Resolution (bits): 16 b
• Sampling Rate (per Second): 21.84k
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Number Of Converters: 2
• Resolution: 16 bit
• Interface Type: Serial (4-Wire, SPI, QSPI, Microwire)
• Voltage Reference: 1.25 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.8 V
• Maximum Power Dissipation: 2051.3 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 1.8 V to 3.6 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MUX register configures the positive and negative
mux inputs and can start an ADC conversion.
the MUX register address byte. S = 1 resets the regis-
ters inside the ADC filter and initiates a conversion or
calibration. The conversion begins immediately after
the eighth MUX register data bit, when S = 1 and when
writing to the MUX register. This allows the new MUX
and ADC register settings to take effect simultaneously
for a new conversion, if STRT = 0 during the last write
to the ADC register. If the S bit is asserted and the
command is a read from the MUX register, the conver-
sion starts immediately after the S bit (ADR0) is clocked
in by the rising edge of SCLK.
of initiating a conversion because only 8 bits are
required. The subsequent MUX register read is valid,
but can be aborted by raising CS with no harmful side
effects. The initial conversion requires four conversion
cycles for valid output data. If CONT = 0 and S = 1, the
ADC stops after a single conversion and holds the
result in the DATA register. If CONT = 1 and S = 1, the
ADC performs continuous conversions at the rate
16-Bit, Data-Acquisition System with ADC, DACs,
MUX Register (Power-On State: 0000 0000)
S (ADR0): Conversion start bit. The S bit is the LSB of
Read the MUX register with S = 1 for the fastest method
Table 8. Selecting the Positive MUX Inputs
X = Don’t care.
POSITIVE MUX
UPIOs, RTC, Voltage Monitors, and Temp Sensor
S (ADR0)
TEMP+
INPUT
AGND
SNO1
SCM1
SNC1
Open
AIN1
FBA
FBB
IN1-
REF
MUXP3
MUXP3
MSB
______________________________________________________________________________________
0
0
0
0
0
0
0
0
1
1
1
1
MUXP2
MUXP2
0
0
0
0
1
1
1
1
0
0
0
1
MUXP1
0
0
1
1
0
0
1
1
0
0
1
X
MUXP1
MUXP0
0
1
0
1
0
1
0
1
0
1
X
X
MUXP0
specified by the RATE<2:0> bits until CONT deasserts
or ADCE deasserts, powering down the ADC. When a
conversion initiates using the S bit, the STRT bit asserts
and deasserts automatically after the initial conversion
completes. Writing to the MUX register with S = 0 caus-
es the MUX settings to change immediately and the
ADC continues in its prior state with its settings unaf-
fected. When the ADC is powered down, MUX inputs
are open.
MUXP<3:0>: MUX positive input bits. These four bits
select one of 10 inputs from the positive MUX to go to the
positive output of the MUX as shown in Table 8. Any
writes to the MUX register take effect immediately once
the LSB (MUXN0) is clocked by the rising edge of SCLK.
MUXN<3:0> MUX negative input bits. These four bits
select one of 10 inputs from the negative MUX to go to
the negative output of the MUX as shown in Table 9. Any
writes to the MUX register take effect immediately once
the LSB (MUXN0) is clocked by the rising edge of SCLK.
The DATA register contains the data from the most
recently completed conversion.
The OFFSET CAL register contains the 24-bit data of
the most recently completed offset calibration.
Table 9. Selecting the Negative MUX Inputs
X = Don’t care.
MUX INPUT
NEGATIVE
TEMP-
AGND
OUTA
SCM2
OUTB
SNO2
SNC2
OUT1
Open
AIN2
REF
MUXN3
MUXN3
MUXN2
0
0
0
0
0
0
0
0
1
1
1
1
MUXN2
0
0
0
0
1
1
1
1
0
0
0
1
MUXN1
MUXN1
0
0
1
1
0
0
1
1
0
0
1
X
MUXN0
LSB
MUXN0
X
X
0
1
0
1
0
1
0
1
0
1
39