MAX11359AETL+T Maxim Integrated Products, MAX11359AETL+T Datasheet - Page 26

• Manufacturer Part Number: MAX11359AETL+T
• Description: IC DAS SYSTEM 16BIT 40-TQFN
• Manufacturer: Maxim Integrated Products
• Type: Data Acquisition System (DAS)r

Specifications of MAX11359AETL+T

• Resolution (bits): 16 b
• Sampling Rate (per Second): 477
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX11359A contains an on-chip digital lowpass fil-
ter that processes the data stream from the modulator
using a SINC
settling time of four output data periods (4 x 200ms).
The MAX11359A has 25% overrange capability built into
the modulator and digital filter:
Figure 4 shows the filter frequency response. The
SINC
times the first notch frequency.
The output data rate for the digital filter corresponds
with the positioning of the first notch of the filter’s fre-
quency response. The notches of the SINC
repeated at multiples of the first notch frequency. The
SINC
100dB at these notches. For example, 50Hz is equal to
five times the first notch frequency and 60Hz is equal to
six times the first notch frequency.
16-Bit Data-Acquisition System with ADC, DAC,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Figure 4. Filter Frequency Response
26
______________________________________________________________________________________
4
4
characteristic -3dB cutoff frequency is 0.228
filter provides an attenuation of better than
-120
-160
-200
H f
-40
-80
( ) =
0
4
0
(sinx/x)
⎡
⎢
⎢
⎢
⎢
⎢
⎣
N
1
20
SIN N
SIN
4
⎛
⎜
⎝
40
response. The SINC
⎛
⎜
⎝
FREQUENCY (Hz)
π
π
f
m
f
f
m
f
60
⎞
⎟
⎠
⎞
⎟
⎠
⎤
⎥
⎥
⎥
⎥
⎥
⎦
4
80
Digital Filtering
100
120
4
filter has a
4
filter are
The MAX11359A incorporates a 10-bit force-sensing
DAC. The DAC’s reference voltage sets the full-scale
range. Program the DACA_OP register using the serial
interface to set the output voltages of the DAC at
OUTA. Connecting resistors in a voltage-divider config-
uration between OUTA, FBA, and GND sets a different
closed-loop gain for the output amplifier (see the
Applications Information section).
The DAC output amplifier typically settles to ±0.5 LSB
from a full-scale transition within 50µs (unity gain and
loaded with 10kΩ in parallel with 200pF). Loads of less
than 1kΩ may degrade performance. See the Typical
Operating Characteristics for the source-and-sink
capability of the DAC output.
The MAX11359A features a software-programmable
shutdown mode for the DAC. Power down DACA by
clearing the DAE bits (see the DACA_OP Register sec-
tion). DAC output OUTA goes high impedance when
powered down. The DAC is normally powered down at
power-on reset.
The charge pump provides > 3V at CPOUT with a maxi-
mum 10mA load. Enable the charge pump through the
PS_VMONS register. The charge pump is powered
from DV
the charge pump and linear regulator. The charge
pump is disabled at power-on reset.
An internal clock drives the charge-pump clock and
ADC clock. The charge pump delivers a maximum
10mA of current to external devices. The droop and the
ripple depend on the clock frequency (f
32.768kHz/2), switch resistances (R
the external capacitors (10µF) along with their respec-
tive ESRs, as shown below.
R
OUT
V
RIPPLE
=
DD
f
CLK F
. See Figures 5 and 6 for block diagrams of
1
V
C
=
DROOP
f
CLK CPOUT
+
2
I
C
OUT
R
=
SWITCH
I
OUT OUT
R
+
+
2
Force-Sense DAC
4
I
OUT
ESR
SWITCH
ESR
Charge Pump
C
F
C
+
CPOUT
ESR
= 5Ω), and
C
CLK
CPOUT
=