MAX186ACWP+ Maxim Integrated Products, MAX186ACWP+ Datasheet - Page 17
![no-image](/images/manufacturer_photos/0/4/417/maxim_integrated_products_sml.jpg)
MAX186ACWP+
Manufacturer Part Number
MAX186ACWP+
Description
IC ADC 12BIT SERIAL 20-SOIC
Manufacturer
Maxim Integrated Products
Type
Data Acquisition System (DAS), ADCr
Datasheet
1.MAX188DCPP.pdf
(24 pages)
Specifications of MAX186ACWP+
Resolution (bits)
12 b
Sampling Rate (per Second)
133k
Data Interface
Serial
Voltage Supply Source
Dual ±
Voltage - Supply
±5V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Package
20SOIC W
Resolution
12 Bit
Sampling Rate
133 KSPS
Architecture
SAR
Number Of Adcs
1
Number Of Analog Inputs
8|4|4
Digital Interface Type
Serial (4-Wire, SPI, QSPI, Microwire)
Input Type
Voltage
Polarity Of Input Voltage
Unipolar|Bipolar
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 12b. Timing Diagram Power-Down Modes, Internal Clock
The SHDN pin places the converter into the full
power-down mode. Unlike with the software shut-down
modes, conversion is not completed. It stops coinci-
dentally with SHDN being brought low. There is no
power-up delay if an external reference is used and is
not shut down. The SHDN pin also selects internal or
external reference compensation (see Table 7).
The MAX186/MAX188 auto power-down modes can
save considerable power when operating at less than
maximum sample rates. The following discussion illus-
trates the various power-down sequences.
Figure 13. MAX186 FULLPD/FASTPD Power-Up Sequence
CLOCK
SSTRB
MODE
MODE
DOUT
DIN
REFADJ
VREF
DIN
1
FULLPD
S X X X X X 1 0
2.5V
0V
4V
0V
0 0
______________________________________________________________________________________
Power-Down Sequencing
CONVERSION
SETS INTERNAL
CLOCK MODE
Hardware Power-Down
(ZEROS)
POWERED UP
COMPLETE CONVERSION SEQUENCE
DATA VALID
1
= RC = 20k x C
FASTPD
INTERNAL CLOCK MODE
2ms WAIT
0 1
REFADJ
S
X
The following examples illustrate two different power-down
sequences. Other combinations of clock rates, compen-
sation modes, and power-down modes may give lowest
power consumption in other applications.
Figure 14a depicts the MAX186 power consumption for
one or eight channel conversions utilizing full
power-down mode and internal reference compensation.
A 0.01µF bypass capacitor at REFADJ forms an RC filter
with the internal 20kΩ reference resistor with a 0.2ms
time constant. To achieve full 12-bit accuracy, 10 time
constants or 2ms are required after power-up. Waiting
2ms in FASTPD mode instead of full power-up will reduce
the power consumption by a factor of 10 or more. This is
achieved by using the sequence shown in Figure 13.
X
Low-Power, 8-Channel,
X
t
BUFFEN
X
1
X
0 0
NOPD
CH1
15µs
SETS FULL
POWER-DOWN
CONVERSION
Serial 12-Bit ADCs
1
1
1
FULLPD
CH7
Conversions/Channel/Second
DATA VALID
0 0
POWER-DOWN
Lowest Power at up to 500
FULL
(ZEROS)
1
FASTPD
S
POWERED
0 1
UP
17