TDA8754HL/14/C1,55 NXP Semiconductors, TDA8754HL/14/C1,55 Datasheet - Page 33
![IC TRPL 8BIT VIDEO ADC 144LQFP](/photos/6/65/66527/tda8754hl14be-s_sml.jpg)
TDA8754HL/14/C1,55
Manufacturer Part Number
TDA8754HL/14/C1,55
Description
IC TRPL 8BIT VIDEO ADC 144LQFP
Manufacturer
NXP Semiconductors
Type
Video ADCr
Datasheet
1.TDA8754HL14C155.pdf
(57 pages)
Specifications of TDA8754HL/14/C1,55
Package / Case
144-LQFP
Resolution (bits)
8 b
Sampling Rate (per Second)
270M
Data Interface
Serial
Voltage Supply Source
Analog and Digital
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Operating Supply Voltage
3 V to 3.6 V
Supply Current
180 mA
Maximum Operating Temperature
+ 70 C
Maximum Power Dissipation
1.3 W
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-2057
935272706551
TDA8754HL14BE-S
935272706551
TDA8754HL14BE-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TDA8754HL/14/C1,55
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
Table 48:
Table 49:
Table 50:
9397 750 14984
Product data sheet
Bit
4
3
2
1
0
Bit
7
6
5
4
3
2
Bit
Symbol
Reset
Access
CLAMP - clamp register (address 15h) bit description
INVERTER - inverter register (address 16h) bit allocation
INVERTER - inverter register (address 16h) bit description
Symbol
CLPSEL1
CLPH
CLPENL
ICLP
CLPT
Symbol
-
COS
CLPS
CKREFOINV
DEOINVRGB
HSOINVRGB
9.15 Inverter register
W
X
7
-
COS
W
6
0
Description
can be used to select the clamp signal; see bit CLPSEL2
inhibits the clamp signal during the Vsynco or coast signal; see bit TSTCOAST
defines if clamp input works on edge or on level
dedicated for test mode; should be forced to logic 0
defines if the test mode of the clamp is active
Description
not used
enables the COAST input signal to be inverted
enables the CLAMP input signal to be inverted
enables the output CKREFO to be inverted
enables the output DEO to be inverted
enables the output HSYNCO to be inverted
0 = PLL reference signal
1 = clamp input
0 = clamp inhibited during Vsynco
1 = clamp active during Vsynco
0 = on edge; for all frequencies (must be preferably chosen)
1 = on level; only for frequencies below 45 MHz to have proper clamp function
0 = not active
1 = active
0 = non-inverted
1 = inverted
0 = non-inverted
1 = inverted
0 = non-inverted
1 = inverted
0 = non-inverted
1 = inverted
0 = non-inverted
1 = inverted
CLPS
W
5
0
CKREFOINV DEOINVRGB HSOINVRGB VSOINVRGB FIELDOINV
Rev. 06 — 16 June 2005
W
4
0
…continued
W
3
0
Triple 8-bit video ADC up to 270 Msps
W
2
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
W
1
0
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W
0
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