DS3904U-020+ Maxim Integrated Products, DS3904U-020+ Datasheet - Page 9

• Manufacturer Part Number: DS3904U-020+
• Description: IC POT NV TRIPLE 128POS 8-USOP
• Manufacturer: Maxim Integrated Products

Specifications of DS3904U-020+

• Taps: 128
• Resistance (ohms): 20K
• Number Of Circuits: 3
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Resistance In Ohms: 20K
• Number Of Pots: Triple
• Taps Per Pot: 128
• Resistance: 20 KOhms
• Wiper Memory: Non Volatile
• Digital Interface: Serial (2-Wire)
• Operating Supply Voltage: 2.7 V to 5.5 V
• Supply Current: 200 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Description/function: Triple 128 Position Nonvolatile Variable Digital Resistor/Switch
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Temperature Coefficient: 125 PPM / C
• Tolerance: 25 %
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Temperature Coefficient: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 2. 2-Wire Data Transfer Protocol
Figure 3. 2-Wire AC Characteristics
The following bus protocol has been defined:
Accordingly, the following bus conditions have been
defined:
SDA
SCL
SDA
SCL
Data transfer can be initiated only when the bus is
not busy.
During data transfer, the data line must remain sta-
ble whenever the clock line is high. Changes in the
data line while the clock line is high are interpreted
as control signals.
CONDITION
START
STOP
t
BUF
START
MSB
1
Triple 128-Position Nonvolatile Digital
t
HD:STA
2
t
LOW
SLAVE ADDRESS
6
_____________________________________________________________________
t
R
t
HD:DAT
7
DIRECTION
t
F
R/W
t
BIT
HIGH
8
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
t
SU:DAT
Variable Resistor/Switch
ACK
9
REPEATED
Bus Not Busy: Both data and clock lines remain
high.
Start Data Transfer: A change in the state of the
data line from high to low while the clock is high
defines a start condition.
Stop Data Transfer: A change in the state of the
data line from low to high while the clock line is
high defines the stop condition.
Data Valid: The state of the data line represents
valid data when, after a start condition, the data line
is stable for the duration of the high period of the
clock signal. The data on the line can be changed
during the low period of the clock signal. There is
START
1
t
SU:STA
t
HD:STA
2
REPEATED IF MORE BYTES
ARE TRANSFERRED
3–7
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
8
ACK
9
t
SP
OR REPEATED
t
CONDITION
CONDITION
SU:STO
START
STOP
9