DS1844S-010+ Maxim Integrated Products, DS1844S-010+ Datasheet - Page 9

• Manufacturer Part Number: DS1844S-010+
• Description: IC POT DIG QUAD 10K 20-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of DS1844S-010+

• Taps: 64
• Resistance (ohms): 10K
• Number Of Circuits: 4
• Temperature Coefficient: 750 ppm/°C Typical
• Memory Type: Volatile
• Interface: 2-Wire or 5-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Resistance In Ohms: 10K
• Number Of Pots: Quad
• Taps Per Pot: 64
• Resistance: 10 KOhms
• Wiper Memory: Volatile
• Digital Interface: Serial (2-Wire, 5-Wire)
• Operating Supply Voltage: 3.3 V, 5 V
• Supply Current: 2.5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5-WIRE SERIAL INTERFACE
AC ELECTRICAL CHARACTERISTICS
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Port Select Setup
R/ W Setup
Clock Frequency
Width of CLK Pulse
Data Setup Time
Data Hold Time
Progapation Delay Time High to Low
Level Clock to Output
CLK Rise Time, CLK Fall Time
RST High to Clock Input High
RST Low from Clock Input High
RST Inactive
All voltages are referenced to ground.
I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V
I
I
appropriate logic levels. Appropriate logic levels specify that logic inputs are within a 0.5-volt of
ground or V
After this period, the first clock pulse is generated.
A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the
V
The maximum t
the SCL.
A fast mode device can be used in a standard mode system, but the requirement t
must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line t
is released.
C
(V
Typical values are for ta = 25°C and nominal supply voltage.
CC
STBY
B
IH MIN
PARAMETER
CC
- total capacitance of one bus line in picofarads, timing referenced to (0.9)(V
specified with SDA pin open.
).
specified with for V
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
CC
for the corresponding inactive state.
HD:DAT
has only to be met if the device does not stretch the LOW period (t
CC
SYMBOL
equal 3.0V and 5.0V and control port logic pins are driven to the
t
t
SETUP
SETUP
t
f
t
t
t
t
t
CDH
t
t
CLK
HLT
RLT
CH
DC
DV
CC
CR
RMAX
9 of 14
MIN
DC
125
30
30
50
30
50
50
0
+ t
SU:DAT
(-40°C to +85°C; V
TYP
= 1000+250=1250 ns before the SCL line
MAX
40
50
5
UNITS
CC
CC
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
=2.7V to 5.5V)
is switched off.
CC
) and (0.1)
SU:DAT
NOTES
14, 21
14, 21
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
14, 15
> 250 ns
LOW
) of