MCP4551T-503E/MS Microchip Technology, MCP4551T-503E/MS Datasheet - Page 49
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MCP4551T-503E/MS
Manufacturer Part Number
MCP4551T-503E/MS
Description
IC POT DGTL 50K SGL 8-MSOP
Manufacturer
Microchip Technology
Datasheet
1.MCP4531-104EMS.pdf
(88 pages)
Specifications of MCP4551T-503E/MS
Package / Case
8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
Taps
257
Resistance (ohms)
50K
Number Of Circuits
1
Temperature Coefficient
150 ppm/°C Typical
Memory Type
Volatile
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Resistance In Ohms
50K
Number Of Pots
Single
Taps Per Pot
256
Resistance
50 KOhms
Wiper Memory
Volatile
Digital Interface
Serial (2-Wire, I2C)
Operating Supply Voltage
2.5 V, 3.3 V, 5 V
Supply Current
2.5 uA
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCP4551T-503E/MS
Manufacturer:
MICROCHIP
Quantity:
12 000
6.2.6
The I
device must be ‘activated’ to operate in high-speed
(3.4 Mbit/s) mode. This is done by the Master sending
a special address byte following the START bit. This
byte is referred to as the high-speed Master Mode
Code (HSMMC).
The MCP45XX/46XX device does not acknowledge
this byte. However, upon receiving this command, the
device switches to HS mode. The device can now com-
municate at up to 3.4 Mbit/s on SDA and SCL lines.
The device will switch out of the HS mode on the next
STOP condition.
The master code is sent as follows:
1.
2.
3.
FIGURE 6-10:
© 2008 Microchip Technology Inc.
S
START condition (S)
High-Speed Master Mode Code (0000 1XXX),
The XXX bits are unique to the high-speed (HS)
mode Master.
No Acknowledge (A)
2
R/W = Read/Write bit
C specification requires that a high-speed mode
F/S-mode
‘0 0 0 0 1 X X X’b
Sr = Repeated Start bit
S = Start bit
A = Acknowledge bit
A = Not Acknowledge bit
P = Stop bit (Stop condition terminates HS Mode)
HS Select Byte
HS MODE
HS Mode Sequence.
A
Sr
HS-mode
‘Slave Address’
Control Byte
MCP453X/455X/463X/465X
R/W
A
Command/Data Byte(s)
After switching to the High-Speed mode, the next
transferred byte is the I
the device to communicate with, and any number of
data bytes plus acknowledgements. The Master
Device can then either issue a Repeated Start bit to
address a different device (at High-Speed) or a Stop bit
to return to Fast/Standard bus speed. After the Stop bit,
any other Master Device (in a Multi-Master system) can
arbitrate for the I
See
sequence.
For more information on the HS mode, or other I
modes, please refer to the Phillips I
6.2.6.1
The slope control on the SDA output is different
between the Fast/Standard Speed and the High-Speed
clock modes of the interface.
6.2.6.2
The pulse gobbler on the SCL pin is automatically
adjusted to suppress spikes < 10 ns during HS mode.
“Data”
Figure 6-10
Slope Control
Pulse Gobbler
A/A
2
for illustration of HS mode command
C bus.
Sr
P
‘Slave Address’ R/W
HS-mode continues
2
C control byte, which specifies
Control Byte
F/S-mode
2
DS22096A-page 49
C specification.
A
2
C