AD5207BRU10 Analog Devices Inc, AD5207BRU10 Datasheet - Page 3

• Manufacturer Part Number: AD5207BRU10
• Description: IC DGTL POT DUAL 256POS 14TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5207BRU10

• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Rohs Status: RoHS non-compliant
• Taps: 256
• Resistance (ohms): 10K
• Number Of Circuits: 2
• Temperature Coefficient: 500 ppm/°C Typical
• Memory Type: Volatile
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V, ±2.2 V ~ 2.7 V
• Operating Temperature: -40°C ~ 125°C
• Resistance In Ohms: 10K
• Peak Reflow Compatible (260 C): No
• Supply Voltage Max: 5.5V
• Leaded Process Compatible: No
• Supply Voltage Min: 2.7V
• Wiper Type: Volatile
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Parameter
INTERFACE TIMING
CHARACTERISTICS
Applies to All Parts
NOTES
10
11
12
The AD5207 contains 474 transistors. Die Size: 67 mil × 69 mil, 4623 sq. mil.
Specifications subject to change without notice.
REV. 0
1
2
3
4
5
6
7
8
9
Typicals represent average readings at 25°C and V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
V
V
INL and DNL are measured at V
specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions.
Resistor Terminals A, B, W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Measured at the A
P
All dynamic characteristics use V
Measured at a V
See timing diagram for location of measured values. All input control voltages are specified with t
1.5 V. Switching characteristics are measured using V
Propagation delay depends on value of V
Input Clock Pulsewidth
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
CS Setup Time
CS High Pulsewidth
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
DISS
SS
AB
= 0 V.
= V
is calculated from (I
DD
, Wiper (V
W
X
pin where an adjacent V
6, 11
terminals. All A
W
) = No connect.
DD
× V
DD
DD
W
). CMOS logic level inputs result in minimum power dissipation.
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
X
= 5 V, V
12
terminals are open-circuited in shut-down mode.
DD
W
, R
(DATA OUT)
SS
pin is making a full-scale voltage change.
(DATA IN)
L
Symbol
t
t
t
t
t
t
t
t
t
= 0 V.
, and C
CH
DS
DH
PD
CSS
CSW
CSH0
CSH1
CS1
V
V
OUT
CLK
SDO
SDI
OUT
CLK
DD
, t
CS
SDI
CS
V
CL
= 5 V, V
DD
DD
0V
1
0
1
0
1
0
L
1
0
1
0
1
0
1
0
; see applications text.
= 5 V.
Figure 1b. Detail Timing Diagram
A1
Ax OR Dx
SS
Figure 1a. Timing Diagram
A'x OR D'x
t
Conditions
Clock Level High or Low
R
= 0 V.
CSS
A0
L
t
= 1 kΩ to 5 V, C
CSH0
D7
t
CH
D6
Ax OR Dx
t
DS
t
D5
A
CL
RDAC REGISTER LOAD
–3–
'
x OR D
D4
t
DH
L
'
x
D3
1LSB ERROR BAND
< 20 pF
D2
R
D1
t
t
= t
CS1
PD_MAX
t
CSH1
t
F
D0
S
= 2 ns (10% to 90% of 3 V) and timed from a voltage level of
t
CSW
1LSB
Min
10
5
5
1
10
10
0
0
10
W
Typ
= V
A
= V
DD
1
DD
/R for both V
and V
Max
25
B
AD5207
= 0 V. DNL
DD
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
= 5 V,